oput.s

avr单片机

L2:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e watchdog_init _watchdog_init fV
	.even
_watchdog_init::
	.dbline -1
	.dbline 46
; }
; //======================================================内部看门狗初始化
; //Watchdog initialisation
; // prescale: 2048K cycles
; void watchdog_init(void)
; {
	.dbline 47
;  WDR(); //this prevents a timout on enabling//
	wdr
	.dbline 48
;  WDTCR = 0x0F; //WATCHDOG ENABLED - dont forget to issue WDRs
	ldi R24,15
	out 0x21,R24
	.dbline -2
L3:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e uart0_init _uart0_init fV
	.even
_uart0_init::
	.dbline -1
	.dbline 60
; }
; 
; 
; //======================================================串口初始化
; //UART0 initialisation
; // desired baud rate:38400
; // actual baud rate:38462 (0.2%)
; // char size: 8 bit
; // parity: Disabled
; 
; void uart0_init(void)
; {
	.dbline 61
;  UCSR0B = 0x00; //disable while setting baud rate
	clr R2
	out 0xa,R2
	.dbline 62
;  UCSR0A = 0x00;
	out 0xb,R2
	.dbline 63
;  UCSR0C = 0x06;
	ldi R24,6
	sts 149,R24
	.dbline 64
;  UBRR0L = 0x19; //set baud rate lo
	ldi R24,25
	out 0x9,R24
	.dbline 65
;  UBRR0H = 0x00; //set baud rate hi
	sts 144,R2
	.dbline 66
;  UCSR0B = 0xB8;
	ldi R24,184
	out 0xa,R24
	.dbline -2
L4:
	.dbline 0 ; func end
	ret
	.dbend
	.area vector(rom, abs)
	.org 76
	jmp _uart0_udre_isr
	.area text(rom, con, rel)
	.dbfile D:\excersize\oput.c
	.dbfunc e uart0_udre_isr _uart0_udre_isr fV
	.even
_uart0_udre_isr::
	st -y,R2
	st -y,R3
	st -y,R24
	st -y,R25
	st -y,R30
	st -y,R31
	in R2,0x3f
	st -y,R2
	.dbline -1
	.dbline 72
; }
; 
; 
; //======================================================串口0发送中断
; #pragma interrupt_handler uart0_udre_isr:20
; void uart0_udre_isr(void){
	.dbline 73
;    if(TxOperateSp0!=TxLoadSp0){
	lds R2,_TxLoadSp0
	lds R3,_TxOperateSp0
	cp R3,R2
	breq L6
	.dbline 73
	.dbline 74
; 	  UDR0=TxBuffer0[TxLoadSp0++]; 
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxLoadSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	out 0xc,R2
	.dbline 75
;    }
	xjmp L7
L6:
	.dbline 76
	.dbline 76
	in R24,0xa
	andi R24,223
	out 0xa,R24
	.dbline 76
L7:
	.dbline -2
L5:
	ld R2,y+
	out 0x3f,R2
	ld R31,y+
	ld R30,y+
	ld R25,y+
	ld R24,y+
	ld R3,y+
	ld R2,y+
	.dbline 0 ; func end
	reti
	.dbend
	.dbfunc e timer0_init _timer0_init fV
	.even
_timer0_init::
	.dbline -1
	.dbline 86
;    else{UCSR0B&=0XDF;}
;    
; }
; 
; 
; //======================================================time0 初始化
; //TIMER0 initialisation - prescale:32
; // WGM: Normal
; // desired value: 1KHz
; // actual value:  1.000KHz (0.0%)
; void timer0_init(void){
	.dbline 87
;  TCCR0 = 0x00; //stop
	clr R2
	out 0x33,R2
	.dbline 88
;  ASSR  = 0x00; //set async mode//同步方式，允许更新计数，比较输出，控制寄存器
	out 0x30,R2
	.dbline 89
;  TCNT0 = 0x83; //set count
	ldi R24,131
	out 0x32,R24
	.dbline 90
;  OCR0  = 0x7D;
	ldi R24,125
	out 0x31,R24
	.dbline 91
;  TCCR0 = 0x05; //start timer//128分频
	ldi R24,5
	out 0x33,R24
	.dbline -2
L8:
	.dbline 0 ; func end
	ret
	.dbend
	.area vector(rom, abs)
	.org 60
	jmp _timer0_comp_isr
	.area text(rom, con, rel)
	.dbfile D:\excersize\oput.c
	.dbfunc e timer0_comp_isr _timer0_comp_isr fV
	.even
_timer0_comp_isr::
	st -y,R24
	st -y,R25
	in R24,0x3f
	st -y,R24
	.dbline -1
	.dbline 95
; }
; //======================================================time0 中断
; #pragma interrupt_handler timer0_comp_isr:16
; void timer0_comp_isr(void){
	.dbline 96
;    TCNT0 = 0x83;
	ldi R24,131
	out 0x32,R24
	.dbline 97
;    T0Count0++;
	lds R24,_T0Count0
	lds R25,_T0Count0+1
	adiw R24,1
	sts _T0Count0+1,R25
	sts _T0Count0,R24
	.dbline 98
;    T0Count1++;
	lds R24,_T0Count1
	lds R25,_T0Count1+1
	adiw R24,1
	sts _T0Count1+1,R25
	sts _T0Count1,R24
	.dbline 99
;    T0Count2++;
	lds R24,_T0Count2
	lds R25,_T0Count2+1
	adiw R24,1
	sts _T0Count2+1,R25
	sts _T0Count2,R24
	.dbline 100
;    T0Count3++; 
	lds R24,_T0Count3
	lds R25,_T0Count3+1
	adiw R24,1
	sts _T0Count3+1,R25
	sts _T0Count3,R24
	.dbline 101
;    T0Count4++;
	lds R24,_T0Count4
	lds R25,_T0Count4+1
	adiw R24,1
	sts _T0Count4+1,R25
	sts _T0Count4,R24
	.dbline -2
L9:
	ld R24,y+
	out 0x3f,R24
	ld R25,y+
	ld R24,y+
	.dbline 0 ; func end
	reti
	.dbend
	.dbfunc e init_devices _init_devices fV
	.even
_init_devices::
	.dbline -1
	.dbline 109
;  //compare occured TCNT0=OCR0
; }
; //======================================================速度中断处理函数
; 
; //======================================================CPU初始化
; //call this routine to initialise all peripherals
; void init_devices(void)
; {
	.dbline 111
;  //stop errant interrupts until set up
;  CLI(); //disable all interrupts
	cli
	.dbline 112
;  XDIV  = 0x00; //xtal divider//系统时钟分频控制寄存器
	clr R2
	out 0x3c,R2
	.dbline 113
;  XMCRA = 0x0E; //external memory//外部存储器控制寄存器
	ldi R24,14
	sts 109,R24
	.dbline 114
;  XMCRB = 0x80;
	ldi R24,128
	sts 108,R24
	.dbline 115
;  mapping_init();
	xcall _mapping_init
	.dbline 116
;  port_init();
	xcall _port_init
	.dbline 119
;  //watchdog_init();
; // timer1_init();
;  timer0_init();
	xcall _timer0_init
	.dbline 123
; 
;  //adc_init();
;  
;  MCUCR = 0xC0;//MCU控制寄存器
	ldi R24,192
	out 0x35,R24
	.dbline 124
;  EICRA = 0x0A; //extended ext ints//外部中断控制寄存器
	ldi R24,10
	sts 106,R24
	.dbline 125
;  EICRB = 0x0F; //extended ext ints
	ldi R24,15
	out 0x3a,R24
	.dbline 126
;  EIMSK = 0x33; //0x03 extended ext enable
	ldi R24,51
	out 0x39,R24
	.dbline 127
;  TIMSK = 0x12; //timer interrupt sources  01:time0
	ldi R24,18
	out 0x37,R24
	.dbline 128
;  ETIMSK = 0x00; //extended timer interrupt sources
	clr R2
	sts 125,R2
	.dbline 129
;  uart0_init();
	xcall _uart0_init
	.dbline 130
;  SEI(); //re-enable interrupts
	sei
	.dbline -2
L10:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e WatchDog _WatchDog fV
	.even
_WatchDog::
	.dbline -1
	.dbline 135
; 	  // MyselfCan0Addr=1;
; 	  // MyselfCan1Addr=2;
; }
; //======================================================看门狗处理函数
; void WatchDog(void){
	.dbline 136
;         DDRE|= 0x08;
	sbi 0x2,3
	.dbline 137
; 		PORTE&= 0xF7;
	in R24,0x3
	andi R24,247
	out 0x3,R24
	.dbline 138
; 		PORTE|= 0x08;
	sbi 0x3,3
	.dbline 139
; 		PORTE&= 0xF7;
	in R24,0x3
	andi R24,247
	out 0x3,R24
	.dbline 140
; 		PORTE|= 0x08;
	sbi 0x3,3
	.dbline 141
; 		PORTE&= 0xF7;
	in R24,0x3
	andi R24,247
	out 0x3,R24
	.dbline 142
; 		PORTE|= 0x08;
	sbi 0x3,3
	.dbline 143
; 		WDR();
	wdr
	.dbline -2
L11:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e set_value _set_value fV
	.even
_set_value::
	.dbline -1
	.dbline 149
;      }
; 
; 
; 
; //===============================================初始设置
; void set_value(void){
	.dbline 153
;    
; //   V_average_incept.Word=0;
;   // Cr_average_incept.Word=0;
;    OutputByte0Reg = 255;
	ldi R24,255
	sts _OutputByte0Reg,R24
	.dbline 154
;    OutputByte1Reg = 255;
	sts _OutputByte1Reg,R24
	.dbline 155
;    OutputByte2Reg = 255;
	sts _OutputByte2Reg,R24
	.dbline -2
L12:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e tx0_int_to_bcd _tx0_int_to_bcd fV
;           head -> R22
;              j -> R10
;              i -> R20,R21
	.even
_tx0_int_to_bcd::
	xcall push_gset3
	movw R20,R16
	.dbline -1
	.dbline 162
; }
; 
; 
; //将int型变量转换为bcd码，并填充到TxBuffer0[]中
; /********************************************************************************/
; void tx0_int_to_bcd(int i)
; {
	.dbline 163
;    UC j,head=0;
	clr R22
	.dbline 164
;    if(i<0){
	cpi R20,0
	ldi R30,0
	cpc R21,R30
	brge L14
	.dbline 164
	.dbline 165
;       i=-i;
	com R20
	com R21
	subi R20,0xFF
	sbci R21,0xFF
	.dbline 166
;       TxBuffer0[TxOperateSp0++]='-';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,45
	std z+0,R24
	.dbline 167
;    }	  
L14:
	.dbline 168
;    j=i/10000;i%=10000;if(j){TxBuffer0[TxOperateSp0++]=j+0x30;head=1;}
	ldi R18,10000
	ldi R19,39
	movw R16,R20
	xcall div16s
	mov R10,R16
	.dbline 168
	ldi R18,10000
	ldi R19,39
	movw R16,R20
	xcall mod16s
	movw R20,R16
	.dbline 168
	tst R10
	breq L16
	.dbline 168
	.dbline 168
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R10
	subi R24,208    ; addi 48
	std z+0,R24
	.dbline 168
	ldi R22,1
	.dbline 168
L16:
	.dbline 169
	ldi R18,1000
	ldi R19,3
	movw R16,R20
	xcall div16s
	mov R10,R16
	.dbline 169
	ldi R18,1000
	ldi R19,3
	movw R16,R20
	xcall mod16s
	movw R20,R16
	.dbline 169
	tst R10
	brne L20
	tst R22
	breq L18
L20:
	.dbline 169
;    j=i/1000;i%=1000;if(j||head){TxBuffer0[TxOperateSp0++]=j+0x30;head=1;}
	.dbline 169
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R10
	subi R24,208    ; addi 48
	std z+0,R24
	.dbline 169
	ldi R22,1
	.dbline 169
L18:
	.dbline 170
	ldi R18,100
	ldi R19,0
	movw R16,R20
	xcall div16s
	mov R10,R16
	.dbline 170
	ldi R18,100
	ldi R19,0
	movw R16,R20
	xcall mod16s
	movw R20,R16
	.dbline 170
	tst R10
	brne L23
	tst R22
	breq L21
L23:
	.dbline 170
;    j=i/100;i%=100;if(j||head){TxBuffer0[TxOperateSp0++]=j+0x30;head=1;}
	.dbline 170
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R10
	subi R24,208    ; addi 48
	std z+0,R24
	.dbline 170
	ldi R22,1
	.dbline 170
L21:
	.dbline 171
	ldi R18,10
	ldi R19,0
	movw R16,R20
	xcall div16s
	mov R10,R16
	.dbline 171
	ldi R18,10
	ldi R19,0
	movw R16,R20
	xcall mod16s
	movw R20,R16
	.dbline 171
	tst R10
	brne L26
	tst R22
	breq L24
L26:
	.dbline 171
;    j=i/10;i%=10;if(j||head){TxBuffer0[TxOperateSp0++]=j+0x30;head=1;}
	.dbline 171
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R10
	subi R24,208    ; addi 48
	std z+0,R24
	.dbline 171
	ldi R22,1
	.dbline 171
L24:
	.dbline 172
;    TxBuffer0[TxOperateSp0++]=i+0x30;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	movw R24,R20
	adiw R24,48
	std z+0,R24
	.dbline -2
L13:
	xcall pop_gset3
	.dbline 0 ; func end
	ret
	.dbsym r head 22 c
	.dbsym r j 10 c
	.dbsym r i 20 I
	.dbend
	.dbfunc e tx0_uc_to_bcd _tx0_uc_to_bcd fV
;           head -> R22
;              j -> R10
;              i -> R20
	.even
_tx0_uc_to_bcd::
	xcall push_gset3
	mov R20,R16
	.dbline -1
	.dbline 178
; }
; /*******************************************************************************
; 将uc型变量转换为bcd码，并填充到TxBuffer0[]中
; ********************************************************************************/
; void tx0_uc_to_bcd(UC i)
; {  
	.dbline 179
;    UC j,head=0;
	clr R22
	.dbline 180
;    j=i/100;i%=100;if(j){TxBuffer0[TxOperateSp0++]=j+0x30;head=1;}
	ldi R17,100
	mov R16,R20
	xcall div8u
	mov R10,R16
	.dbline 180
	ldi R17,100
	mov R16,R20
	xcall mod8u
	mov R20,R16
	.dbline 180
	tst R10
	breq L28
	.dbline 180
	.dbline 180
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R10
	subi R24,208    ; addi 48
	std z+0,R24
	.dbline 180
	ldi R22,1
	.dbline 180
L28:
	.dbline 181
	ldi R17,10
	mov R16,R20
	xcall div8u
	mov R10,R16
	.dbline 181
	ldi R17,10
	mov R16,R20
	xcall mod8u
	mov R20,R16
	.dbline 181
	tst R10
	brne L32
	tst R22
	breq L30
L32:
	.dbline 181
;    j=i/10;i%=10;if(j||head){TxBuffer0[TxOperateSp0++]=j+0x30;head=1;}
	.dbline 181
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R10
	subi R24,208    ; addi 48
	std z+0,R24
	.dbline 181
	ldi R22,1
	.dbline 181
L30:
	.dbline 182
;    TxBuffer0[TxOperateSp0++]=i+0x30;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	mov R24,R20
	subi R24,208    ; addi 48