or_gate.vhd

来自「Viertex 2 开发板的接口程序」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity or_gate is
  
  port (
    In0 : in  std_logic;
    In1 : in  std_logic;
    Output : out std_logic);

end or_gate;


architecture behavioral of or_gate is

begin

  Output <= In0 or In1;

end behavioral;