plb_at_v2_1_0.mpd

Viertex 2 开发板的接口程序

 

BEGIN plb_at
OPTION  IPTYPE=PERIPHERAL
OPTION  STYLE=BLACKBOX
OPTION  IMP_NETLIST=TRUE

OPTION SIM_MODELS = BEHAVIORAL 

# Define bus interfaces 
BUS_INTERFACE BUS=SPLB, BUS_STD=PLB, BUS_TYPE=SLAVE 

# Generics for vhdl or parameters for verilog 
PARAMETER C_NUM_MASTERS = 8, DT=integer, BUS=SPLB
PARAMETER C_BASEADDR = 0xA001_0000, DT=std_logic_vector, MIN_SIZE=0x100, BUS=SPLB 
PARAMETER C_HIGHADDR = 0xA001_003F, DT=std_logic_vector, BUS=SPLB 
PARAMETER C_PLB_DWIDTH = 64, DT=integer, BUS=SPLB
PARAMETER C_PLB_AWIDTH = 32, DT=integer, BUS=SPLB
PARAMETER C_PLB_MID_WIDTH = 3, DT=integer, BUS=SPLB

# Global ports 
PORT PLB_Clk = "", DIR=IN, SIGIS=CLK, BUS=SPLB
PORT PLB_Rst = PLB_Rst, DIR=IN, BUS=SPLB

# PLB slave signals
PORT Sl_addrAck = Sl_addrAck, DIR=OUT, BUS=SPLB
PORT Sl_MErr = Sl_MErr, DIR=OUT, VEC=[0:C_NUM_MASTERS-1], BUS=SPLB
PORT Sl_MBusy = Sl_MBusy, DIR=OUT, VEC=[0:C_NUM_MASTERS-1], BUS=SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR=OUT, BUS=SPLB
PORT Sl_rdComp = Sl_rdComp, DIR=OUT, BUS=SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR=OUT, BUS=SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR=OUT, VEC=[0:C_PLB_DWIDTH-1], BUS=SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR=OUT, VEC=[0:3], BUS=SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR=OUT, BUS=SPLB
PORT Sl_SSize = Sl_SSize, DIR=OUT, VEC=[0:1], BUS=SPLB
PORT Sl_wait = Sl_wait, DIR=OUT, BUS=SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR=OUT, BUS=SPLB
PORT Sl_wrComp = Sl_wrComp, DIR=OUT, BUS=SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR=OUT, BUS=SPLB

# PLB output signals
PORT PLB_ABus = PLB_ABus, DIR=IN, VEC=[0:C_PLB_AWIDTH-1], BUS=SPLB
PORT PLB_BE = PLB_BE, DIR=IN, VEC=[0:(C_PLB_DWIDTH/8)-1], BUS=SPLB
PORT PLB_PAValid = PLB_PAValid, DIR=IN, BUS=SPLB
PORT PLB_RNW = PLB_RNW, DIR=IN, BUS=SPLB
PORT PLB_abort = PLB_abort, DIR=IN, BUS=SPLB
PORT PLB_busLock = PLB_busLock, DIR=IN , BUS=SPLB
PORT PLB_compress = PLB_compress, DIR=IN, BUS=SPLB
PORT PLB_guarded = PLB_guarded, DIR=IN, BUS=SPLB
PORT PLB_lockErr = PLB_lockErr, DIR=IN, BUS=SPLB
PORT PLB_masterID = PLB_masterID, DIR=IN, VEC=[0:C_PLB_MID_WIDTH-1], BUS=SPLB
PORT PLB_MSize = PLB_MSize, DIR=IN, VEC=[0:1], BUS=SPLB
PORT PLB_ordered = PLB_ordered, DIR=IN, BUS=SPLB
PORT PLB_pendPri = PLB_pendPri, DIR=IN, VEC=[0:1], BUS=SPLB
PORT PLB_pendReq = PLB_pendReq, DIR=IN, BUS=SPLB
PORT PLB_reqPri = PLB_reqPri, DIR=IN, VEC=[0:1], BUS=SPLB
PORT PLB_size = PLB_size, DIR=IN, VEC=[0:3], BUS=SPLB
PORT PLB_type = PLB_type, DIR=IN, VEC=[0:2], BUS=SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR=IN, BUS=SPLB
PORT PLB_SAValid = PLB_SAValid, DIR=IN, BUS=SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR=IN, BUS=SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR=IN, BUS=SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR=IN, VEC=[0:C_PLB_DWIDTH-1], BUS=SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR=IN, BUS=SPLB

# PLB_AT signals 
PORT TXP             = "", DIR=OUT, VEC=[2:0],IOB_STATE=BUF
PORT TXN             = "", DIR=OUT, VEC=[2:0], IOB_STATE=BUF
PORT RXP             = "", DIR=IN, VEC=[2:0], IOB_STATE=BUF
PORT RXN             = "", DIR=IN, VEC=[2:0], IOB_STATE=BUF
PORT bref_clk_buffered  = "", DIR=IN
PORT all_mgts_pwd_dn = "", DIR=OUT


END