📄 coregen_fifo.edn
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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2003 12 17 19 41 52)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.1i"))))
(comment "
This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of
design files limited to Xilinx devices or technologies. Use
with non-Xilinx devices or technologies is expressly prohibited
and immediately terminates your license.
XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE.
Xilinx products are not intended for use in life support
appliances, devices, or systems. Use in such applications are
expressly prohibited.
(c) Copyright 1995-2003 Xilinx, Inc.
All rights reserved.
")
(comment "Core parameters: ")
(comment "c_read_data_width = 19 ")
(comment "c_has_wr_ack = 0 ")
(comment "c_dcount_width = 1 ")
(comment "c_has_wr_err = 0 ")
(comment "c_wr_err_low = 1 ")
(comment "c_wr_ack_low = 1 ")
(comment "c_enable_rlocs = 0 ")
(comment "c_has_dcount = 0 ")
(comment "c_rd_err_low = 1 ")
(comment "c_rd_ack_low = 1 ")
(comment "InstanceName = coregen_fifo ")
(comment "c_read_depth = 16 ")
(comment "c_has_rd_ack = 0 ")
(comment "c_write_depth = 16 ")
(comment "c_ports_differ = 0 ")
(comment "c_memory_type = 1 ")
(comment "c_write_data_width = 19 ")
(comment "c_has_rd_err = 0 ")
(external xilinxun (edifLevel 0)
(technology (numberDefinition))
(cell VCC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
(cell GND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell FDRE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDSE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port S (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell LUT4 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXCY (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port DI (direction INPUT))
(port CI (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell RAMB16_S36_S36 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port WEA (direction INPUT))
(port ENA (direction INPUT))
(port SSRA (direction INPUT))
(port CLKA (direction INPUT))
(port (rename DIA_0_ "DIA<0>") (direction INPUT))
(port (rename DIA_1_ "DIA<1>") (direction INPUT))
(port (rename DIA_2_ "DIA<2>") (direction INPUT))
(port (rename DIA_3_ "DIA<3>") (direction INPUT))
(port (rename DIA_4_ "DIA<4>") (direction INPUT))
(port (rename DIA_5_ "DIA<5>") (direction INPUT))
(port (rename DIA_6_ "DIA<6>") (direction INPUT))
(port (rename DIA_7_ "DIA<7>") (direction INPUT))
(port (rename DIA_8_ "DIA<8>") (direction INPUT))
(port (rename DIA_9_ "DIA<9>") (direction INPUT))
(port (rename DIA_10_ "DIA<10>") (direction INPUT))
(port (rename DIA_11_ "DIA<11>") (direction INPUT))
(port (rename DIA_12_ "DIA<12>") (direction INPUT))
(port (rename DIA_13_ "DIA<13>") (direction INPUT))
(port (rename DIA_14_ "DIA<14>") (direction INPUT))
(port (rename DIA_15_ "DIA<15>") (direction INPUT))
(port (rename DIA_16_ "DIA<16>") (direction INPUT))
(port (rename DIA_17_ "DIA<17>") (direction INPUT))
(port (rename DIA_18_ "DIA<18>") (direction INPUT))
(port (rename DIA_19_ "DIA<19>") (direction INPUT))
(port (rename DIA_20_ "DIA<20>") (direction INPUT))
(port (rename DIA_21_ "DIA<21>") (direction INPUT))
(port (rename DIA_22_ "DIA<22>") (direction INPUT))
(port (rename DIA_23_ "DIA<23>") (direction INPUT))
(port (rename DIA_24_ "DIA<24>") (direction INPUT))
(port (rename DIA_25_ "DIA<25>") (direction INPUT))
(port (rename DIA_26_ "DIA<26>") (direction INPUT))
(port (rename DIA_27_ "DIA<27>") (direction INPUT))
(port (rename DIA_28_ "DIA<28>") (direction INPUT))
(port (rename DIA_29_ "DIA<29>") (direction INPUT))
(port (rename DIA_30_ "DIA<30>") (direction INPUT))
(port (rename DIA_31_ "DIA<31>") (direction INPUT))
(port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
(port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
(port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
(port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
(port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
(port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
(port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
(port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
(port (rename DOA_8_ "DOA<8>") (direction OUTPUT))
(port (rename DOA_9_ "DOA<9>") (direction OUTPUT))
(port (rename DOA_10_ "DOA<10>") (direction OUTPUT))
(port (rename DOA_11_ "DOA<11>") (direction OUTPUT))
(port (rename DOA_12_ "DOA<12>") (direction OUTPUT))
(port (rename DOA_13_ "DOA<13>") (direction OUTPUT))
(port (rename DOA_14_ "DOA<14>") (direction OUTPUT))
(port (rename DOA_15_ "DOA<15>") (direction OUTPUT))
(port (rename DOA_16_ "DOA<16>") (direction OUTPUT))
(port (rename DOA_17_ "DOA<17>") (direction OUTPUT))
(port (rename DOA_18_ "DOA<18>") (direction OUTPUT))
(port (rename DOA_19_ "DOA<19>") (direction OUTPUT))
(port (rename DOA_20_ "DOA<20>") (direction OUTPUT))
(port (rename DOA_21_ "DOA<21>") (direction OUTPUT))
(port (rename DOA_22_ "DOA<22>") (direction OUTPUT))
(port (rename DOA_23_ "DOA<23>") (direction OUTPUT))
(port (rename DOA_24_ "DOA<24>") (direction OUTPUT))
(port (rename DOA_25_ "DOA<25>") (direction OUTPUT))
(port (rename DOA_26_ "DOA<26>") (direction OUTPUT))
(port (rename DOA_27_ "DOA<27>") (direction OUTPUT))
(port (rename DOA_28_ "DOA<28>") (direction OUTPUT))
(port (rename DOA_29_ "DOA<29>") (direction OUTPUT))
(port (rename DOA_30_ "DOA<30>") (direction OUTPUT))
(port (rename DOA_31_ "DOA<31>") (direction OUTPUT))
(port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
(port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
(port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
(port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
(port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
(port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
(port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
(port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
(port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
(port (rename DIPA_0_ "DIPA<0>") (direction INPUT))
(port (rename DIPA_1_ "DIPA<1>") (direction INPUT))
(port (rename DIPA_2_ "DIPA<2>") (direction INPUT))
(port (rename DIPA_3_ "DIPA<3>") (direction INPUT))
(port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT))
(port (rename DOPA_1_ "DOPA<1>") (direction OUTPUT))
(port (rename DOPA_2_ "DOPA<2>") (direction OUTPUT))
(port (rename DOPA_3_ "DOPA<3>") (direction OUTPUT))
(port WEB (direction INPUT))
(port ENB (direction INPUT))
(port SSRB (direction INPUT))
(port CLKB (direction INPUT))
(port (rename DIB_0_ "DIB<0>") (direction INPUT))
(port (rename DIB_1_ "DIB<1>") (direction INPUT))
(port (rename DIB_2_ "DIB<2>") (direction INPUT))
(port (rename DIB_3_ "DIB<3>") (direction INPUT))
(port (rename DIB_4_ "DIB<4>") (direction INPUT))
(port (rename DIB_5_ "DIB<5>") (direction INPUT))
(port (rename DIB_6_ "DIB<6>") (direction INPUT))
(port (rename DIB_7_ "DIB<7>") (direction INPUT))
(port (rename DIB_8_ "DIB<8>") (direction INPUT))
(port (rename DIB_9_ "DIB<9>") (direction INPUT))
(port (rename DIB_10_ "DIB<10>") (direction INPUT))
(port (rename DIB_11_ "DIB<11>") (direction INPUT))
(port (rename DIB_12_ "DIB<12>") (direction INPUT))
(port (rename DIB_13_ "DIB<13>") (direction INPUT))
(port (rename DIB_14_ "DIB<14>") (direction INPUT))
(port (rename DIB_15_ "DIB<15>") (direction INPUT))
(port (rename DIB_16_ "DIB<16>") (direction INPUT))
(port (rename DIB_17_ "DIB<17>") (direction INPUT))
(port (rename DIB_18_ "DIB<18>") (direction INPUT))
(port (rename DIB_19_ "DIB<19>") (direction INPUT))
(port (rename DIB_20_ "DIB<20>") (direction INPUT))
(port (rename DIB_21_ "DIB<21>") (direction INPUT))
(port (rename DIB_22_ "DIB<22>") (direction INPUT))
(port (rename DIB_23_ "DIB<23>") (direction INPUT))
(port (rename DIB_24_ "DIB<24>") (direction INPUT))
(port (rename DIB_25_ "DIB<25>") (direction INPUT))
(port (rename DIB_26_ "DIB<26>") (direction INPUT))
(port (rename DIB_27_ "DIB<27>") (direction INPUT))
(port (rename DIB_28_ "DIB<28>") (direction INPUT))
(port (rename DIB_29_ "DIB<29>") (direction INPUT))
(port (rename DIB_30_ "DIB<30>") (direction INPUT))
(port (rename DIB_31_ "DIB<31>") (direction INPUT))
(port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
(port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
(port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
(port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
(port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
(port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
(port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
(port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
(port (rename DOB_8_ "DOB<8>") (direction OUTPUT))
(port (rename DOB_9_ "DOB<9>") (direction OUTPUT))
(port (rename DOB_10_ "DOB<10>") (direction OUTPUT))
(port (rename DOB_11_ "DOB<11>") (direction OUTPUT))
(port (rename DOB_12_ "DOB<12>") (direction OUTPUT))
(port (rename DOB_13_ "DOB<13>") (direction OUTPUT))
(port (rename DOB_14_ "DOB<14>") (direction OUTPUT))
(port (rename DOB_15_ "DOB<15>") (direction OUTPUT))
(port (rename DOB_16_ "DOB<16>") (direction OUTPUT))
(port (rename DOB_17_ "DOB<17>") (direction OUTPUT))
(port (rename DOB_18_ "DOB<18>") (direction OUTPUT))
(port (rename DOB_19_ "DOB<19>") (direction OUTPUT))
(port (rename DOB_20_ "DOB<20>") (direction OUTPUT))
(port (rename DOB_21_ "DOB<21>") (direction OUTPUT))
(port (rename DOB_22_ "DOB<22>") (direction OUTPUT))
(port (rename DOB_23_ "DOB<23>") (direction OUTPUT))
(port (rename DOB_24_ "DOB<24>") (direction OUTPUT))
(port (rename DOB_25_ "DOB<25>") (direction OUTPUT))
(port (rename DOB_26_ "DOB<26>") (direction OUTPUT))
(port (rename DOB_27_ "DOB<27>") (direction OUTPUT))
(port (rename DOB_28_ "DOB<28>") (direction OUTPUT))
(port (rename DOB_29_ "DOB<29>") (direction OUTPUT))
(port (rename DOB_30_ "DOB<30>") (direction OUTPUT))
(port (rename DOB_31_ "DOB<31>") (direction OUTPUT))
(port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
(port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
(port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
(port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
(port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
(port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
(port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
(port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
(port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
(port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
(port (rename DIPB_1_ "DIPB<1>") (direction INPUT))
(port (rename DIPB_2_ "DIPB<2>") (direction INPUT))
(port (rename DIPB_3_ "DIPB<3>") (direction INPUT))
(port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
(port (rename DOPB_1_ "DOPB<1>") (direction OUTPUT))
(port (rename DOPB_2_ "DOPB<2>") (direction OUTPUT))
(port (rename DOPB_3_ "DOPB<3>") (direction OUTPUT))
)
)
)
(cell XORCY (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port LI (direction INPUT))
(port CI (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell coregen_fifo
(cellType GENERIC) (view view_1 (viewType NETLIST)
(interface
(port ( rename clk "clk") (direction INPUT))
(port ( rename sinit "sinit") (direction INPUT))
(port ( rename din_18_ "din<18>") (direction INPUT))
(port ( rename din_17_ "din<17>") (direction INPUT))
(port ( rename din_16_ "din<16>") (direction INPUT))
(port ( rename din_15_ "din<15>") (direction INPUT))
(port ( rename din_14_ "din<14>") (direction INPUT))
(port ( rename din_13_ "din<13>") (direction INPUT))
(port ( rename din_12_ "din<12>") (direction INPUT))
(port ( rename din_11_ "din<11>") (direction INPUT))
(port ( rename din_10_ "din<10>") (direction INPUT))
(port ( rename din_9_ "din<9>") (direction INPUT))
(port ( rename din_8_ "din<8>") (direction INPUT))
(port ( rename din_7_ "din<7>") (direction INPUT))
(port ( rename din_6_ "din<6>") (direction INPUT))
(port ( rename din_5_ "din<5>") (direction INPUT))
(port ( rename din_4_ "din<4>") (direction INPUT))
(port ( rename din_3_ "din<3>") (direction INPUT))
(port ( rename din_2_ "din<2>") (direction INPUT))
(port ( rename din_1_ "din<1>") (direction INPUT))
(port ( rename din_0_ "din<0>") (direction INPUT))
(port ( rename wr_en "wr_en") (direction INPUT))
(port ( rename rd_en "rd_en") (direction INPUT))
(port ( rename dout_18_ "dout<18>") (direction OUTPUT))
(port ( rename dout_17_ "dout<17>") (direction OUTPUT))
(port ( rename dout_16_ "dout<16>") (direction OUTPUT))
(port ( rename dout_15_ "dout<15>") (direction OUTPUT))
(port ( rename dout_14_ "dout<14>") (direction OUTPUT))
(port ( rename dout_13_ "dout<13>") (direction OUTPUT))
(port ( rename dout_12_ "dout<12>") (direction OUTPUT))
(port ( rename dout_11_ "dout<11>") (direction OUTPUT))
(port ( rename dout_10_ "dout<10>") (direction OUTPUT))
(port ( rename dout_9_ "dout<9>") (direction OUTPUT))
(port ( rename dout_8_ "dout<8>") (direction OUTPUT))
(port ( rename dout_7_ "dout<7>") (direction OUTPUT))
(port ( rename dout_6_ "dout<6>") (direction OUTPUT))
(port ( rename dout_5_ "dout<5>") (direction OUTPUT))
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