at_xst.prj

来自「Viertex 2 开发板的接口程序」· PRJ 代码 · 共 44 行

VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/synth_defs.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/coregen_fifo.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/AT_CONFIG.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/VirtexIIpLib.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/LED_PWM.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/LED_Fader.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/ck_aurora_2_bref.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/VirtexIIpBoardInterface.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/PatternLib.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/PatternGenerator.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/PatternFollower.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/Gigabit_TX.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/Gigabit_RX.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/AURORA_201.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/aurora_lane.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/channel_error_detect.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/channel_init_sm.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/chbond_count_dec.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/error_detect.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/global_logic.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/idle_and_ver_gen.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/lane_init_sm.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/phase_align.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/rx_ll.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/rx_ll_pdu_datapath.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/sym_dec.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/sym_gen.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/tx_ll.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/tx_ll_control.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/tx_ll_datapath.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/rx_ll_nfc.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/ufc_filter.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/rx_ll_ufc_datapath.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AG_201/201_ufc_nfci/standard_cc_module.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/Echo.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/NFCThrottle.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/UFC_TX.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/UFC_RX.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/VirtexIIpAT.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/MGTBoardAT.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/plb_ipif_slv_sram.v
VERILOG plb_at_v1_01_a C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\plb_at_v1_01_a/hdl/verilog/AT_EDK/plb_at.v