command_fifo.vhd

Viertex 2 开发板的接口程序

  component RAMB16_S36
    generic (
      INIT       : bit_vector := X"000000000";
      SRVAL      : bit_vector := X"000000000";
      write_mode : string     := "WRITE_FIRST";
  
      INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_00  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_01  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_02  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_03  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_04  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_05  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_06  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_07  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_08  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_09  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0A  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0B  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0C  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0D  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0E  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0F  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_10  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_11  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_12  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_13  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_14  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_15  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_16  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_17  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_18  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_19  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_1A  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_1B  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_1C  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_1D  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_1E  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_1F  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_20  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_21  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_22  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_23  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_24  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_25  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_26  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_27  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_28  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_29  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_2A  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_2B  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_2C  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_2D  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_2E  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_2F  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_30  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_31  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_32  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_33  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_34  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_35  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_36  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_37  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_38  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_39  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_3A  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_3B  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_3C  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_3D  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_3E  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_3F  : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
      );
  
    port (
      DO   : out std_logic_vector (31 downto 0);
      DOP  : out std_logic_vector (3 downto 0);
      
      ADDR : in  std_logic_vector (8 downto 0);
      CLK  : in  std_ulogic;
      DI   : in  std_logic_vector (31 downto 0);
      DIP  : in  std_logic_vector (3 downto 0);
      EN   : in  std_ulogic;
      SSR  : in  std_ulogic;
      WE   : in  std_ulogic
      );
  
  end component;

  signal xram_di : std_logic_vector(31 downto 0);    -- BlockRAM data in (zero)
  signal command_addr : unsigned(8 downto 0);    -- BlockRAM data in (zero)
  signal xram_addr : std_logic_vector(8 downto 0);    -- BlockRAM data in (zero)
  signal xram_dip : std_logic_vector(3 downto 0);    -- BlockRAM data in (zero)
  signal xram_dop : std_logic_vector(3 downto 0);    -- BlockRAM data out
  signal xram_en : std_logic;                        -- BlockRAM enable (always on)
  signal xram_we : std_logic;                        -- BlockRAM write enable (zero)
  signal xram_reset : std_logic;                     -- BlockRAM reset (zero)
  signal xram_do : std_logic_vector(31 downto 0);
begin
  
  -- address (need to define)
  block_ram_address_PROCESS : process (Clk) is
  begin
    if Clk'event and Clk = '1' then
      if Reset = '1' then
        command_addr <= (others => '0');
      elsif NextCommand = '1' then
        command_addr <= command_addr + 1;
      end if;
    end if;
  end process;
  
  -- Define input signals to BlockRam
  xram_di <= (others => '0');           -- no data in
  xram_dip <= (others => '0');          -- 2-bit data (not used)
  xram_en <= '1';                       -- always enabled
  xram_we <= '0';                       -- do not need to write
  xram_reset <= '0';                  

  Data <= xram_do(15 downto 0);
  Address <= xram_do(22 downto 16);
  ValidCommand <= xram_do(31);
  
  -- Instance the BlockRam
  u1: RAMB16_S36
--translate_off
-- Note that the these generic map values are used for simulation
-- only. To insure that the simulation matches the actual ram values,
-- make sure that the attributes used above are the same as the
-- generics used below.
  generic map (
    INIT_00 =>
    X"80200001801c0008801a04048018080880040808800a80008002080880000000",
    INIT_01 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_02 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_03 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_04 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_05 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_06 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_07 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_08 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_09 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0a =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0b =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0c =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0d =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0e =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_0f =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_10 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_11 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_12 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_13 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_14 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_15 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_16 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_17 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_18 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_19 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1a =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1b =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1c =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1d =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1e =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_1f =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_20 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_21 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_22 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_23 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_24 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_25 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_26 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_27 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_28 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_29 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2a =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2b =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2c =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2d =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2e =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_2f =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_30 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_31 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_32 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_33 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_34 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_35 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_36 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_37 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_38 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_39 =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3a =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3b =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3c =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3d =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3e =>
       X"0000000000000000000000000000000000000000000000000000000000000000",
    INIT_3f =>
       X"0000000000000000000000000000000000000000000000000000000000000000"

  )
--translate_on
    port map(
           di => xram_di,
           dip => xram_dip,
           addr => xram_addr,
           do => xram_do,
           dop => xram_dop,
           clk => clk,
           SSR => xram_reset,
           EN => xram_en,
           WE => xram_we
         );
    xram_addr <= CONV_STD_LOGIC_VECTOR(command_addr, command_addr'length);

  CommandNum <= xram_addr;
  
end architecture IMP;