📄 hw_bist.srs
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#
#
#
# Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jun 17 17:15:57 2005
#
#
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#CUR:"C:\\xup_v2pro_dev_brd\\lib\\XilinxProcessorIP\\pcores\\hw_bist_v1_01_c\\synplicity_build\\bitreg.v":1108675588l
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#CUR:"C:\\xup_v2pro_dev_brd\\lib\\XilinxProcessorIP\\pcores\\hw_bist_v1_01_c\\synplicity_build\\AUDIO_LEDS_PB_SWITCHES.v":1108675588l
#CUR:"C:\\xup_v2pro_dev_brd\\lib\\XilinxProcessorIP\\pcores\\hw_bist_v1_01_c\\synplicity_build\\AUDIO_LEDS_PB_SWITCHES.v":1108675588l
#CUR:"C:\\xup_v2pro_dev_brd\\lib\\XilinxProcessorIP\\pcores\\hw_bist_v1_01_c\\synplicity_build\\HW_BIST.v":1108675588l
#CUR:"C:\\xup_v2pro_dev_brd\\lib\\XilinxProcessorIP\\pcores\\hw_bist_v1_01_c\\synplicity_build\\HW_BIST.v":1108675588l
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\BLACK_BOXES.v"; # file 0
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CLOCK_GEN.v"; # file 1
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\EXPANSION_PORTS.v"; # file 2
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\VIDEO_RAM.v"; # file 3
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\COLOR_BARS.v"; # file 4
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\VIDEO_OUT.v"; # file 5
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\RAMP.v"; # file 6
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SVGA_TIMING_GENERATION.v"; # file 7
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SVGA_DEFINES.v"; # file 8
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SVGA_DEFINES.v"; # file 9
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\ps2_keyboard_interface.v"; # file 10
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\PS2.v"; # file 11
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHAR_RAM.v"; # file 12
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHAR_GEN_ROM.v"; # file 13
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHARACTER_MODE.v"; # file 14
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\special_clk_div.v"; # file 15
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\ONEWIRE_IFACE.v"; # file 16
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\defines.v"; # file 17
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\HEX_2_ASCII.V"; # file 18
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\jcnt2.v"; # file 19
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\jcnt1.v"; # file 20
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\crcreg.v"; # file 21
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\sr2.v"; # file 22
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\sr1.v"; # file 23
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\parallel_sn_data.v"; # file 24
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\bitreg.v"; # file 25
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\ONEWIRE_MASTER.v"; # file 26
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SSN.v"; # file 27
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHAR_MODE.v"; # file 28
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\AUDIO_LEDS_PB_SWITCHES.v"; # file 29
f "C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\HW_BIST.v"; # file 30
@E
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_uS=QAv_taB_pihs;
R4@@:(4.:4n:..(:4FRIsQ RAtzwRsPCHoDFR11Ya_ vBBpmiz_Awm
S= OD4_jjHSM
QY=11va _mBpB
i;s@R@4d:4.::n4:d..IcRFRs QwAztCRPsFHDoYR11va q_B BBpmiz_Awm
S= ODdH._MQ
S=twuqY_11va q_B BBpmis;
R4@@:U4d:46:d4U:(FRIsA RzRwtPHCsDRFo1_Y1BBpmiz_Awm
S=j_4jxv]_FODOS
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