hw_bist.tlg

Viertex 2 开发板的接口程序

Selecting top level module HW_BIST
Synthesizing module IBUFGDS
Synthesizing module IBUFG
Synthesizing module BUFG
Synthesizing module DCM
Synthesizing module SRL16
Synthesizing module CLOCK_GEN
Synthesizing module CLOCK_AUDIO_PB_SWITCH_TEST
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\AUDIO_LEDS_PB_SWITCHES.v":143:14:143:21|Removing redundant assignment
Synthesizing module IOBUF
Synthesizing module EXPANSION_PORT_TEST
@W: CL159 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\EXPANSION_PORTS.v":62:6:62:20|Input sft_test_enable is unused
Synthesizing module ps2_keyboard_interface
@N: CL201 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\ps2_keyboard_interface.v":302:0:302:5|Trying to extract state machine for register m1_state
Extracted state machine for register m1_state
State machine has 14 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1100
   1101
   1110
Synthesizing module PS2
Synthesizing module SPECIAL_CLK_DIVIDER
Synthesizing module SR1
Synthesizing module SR2
Synthesizing module JCNT1
Synthesizing module JCNT2
Synthesizing module BITREG
Synthesizing module PARALLEL_SN_DATA
Synthesizing module CRCReg
Synthesizing module ONEWIRE_MASTER
@N: CL201 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\ONEWIRE_MASTER.v":498:0:498:5|Trying to extract state machine for register PRESENT_STATE
Extracted state machine for register PRESENT_STATE
State machine has 6 reachable states with original encodings of:
   000
   001
   011
   100
   110
   111
Synthesizing module ONEWIRE_IFACE
Synthesizing module HEX_2_ASCII
Synthesizing module SILICON_SERIAL_NUMBER
Synthesizing module RAMB16_S2_S2
Synthesizing module VIDEO_RAM
Synthesizing module COLOR_BARS
Synthesizing module RAMP
@W: CL159 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\RAMP.v":52:6:52:16|Input pixel_clock is unused
Synthesizing module CHAR_RAM
Synthesizing module RAMB16_S9
Synthesizing module CHAR_GEN_ROM
Synthesizing module CHARACTER_MODE
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHARACTER_MODE.v":190:35:190:61|Removing redundant assignment
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHARACTER_MODE.v":205:31:205:53|Removing redundant assignment
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHARACTER_MODE.v":210:32:210:58|Removing redundant assignment
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHARACTER_MODE.v":211:28:211:50|Removing redundant assignment
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\CHARACTER_MODE.v":212:13:212:20|Removing redundant assignment
Synthesizing module CHAR_MODE
Synthesizing module OFDDRTRSE
Synthesizing module VIDEO_OUT
@W: CL159 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\VIDEO_OUT.v":89:8:89:17|Input comp_synch is unused
Synthesizing module SVGA_TIMING_GENERATION
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SVGA_TIMING_GENERATION.v":361:26:361:43|Removing redundant assignment
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SVGA_TIMING_GENERATION.v":367:19:367:28|Removing redundant assignment
@N: CG179 :"C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\synplicity_build\SVGA_TIMING_GENERATION.v":373:27:373:44|Removing redundant assignment
Synthesizing module HW_BIST