hw_bist.srr

Viertex 2 开发板的接口程序

@W: BN116 :"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\svga_timing_generation.v":347:0:347:5|Removing sequential instance SVGA_TIMING_GENERATION.char_count[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W: BN116 :"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\svga_timing_generation.v":347:0:347:5|Removing sequential instance SVGA_TIMING_GENERATION.line_start_address[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W: BN116 :"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\ps2.v":119:24:119:45|Removing sequential instance PS2.ps2_keyboard_interface.m1_state[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
@W: BN116 :"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\ps2.v":144:24:144:42|Removing sequential instance PS2.ps2_mouse_interface.m1_state[3] of view:UNILIB.FDRE(PRIM) because there are no references to its outputs 
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.HW_BIST(verilog):
No nets needed buffering.

@N: FX164 |The option to pack flops in the IOB has not been specified 
Writing Analyst data base C:\xup_v2pro_dev_brd\lib\XilinxProcessorIP\pcores\hw_bist_v1_01_c\netlist\hw_bist.srm
Writing EDIF Netlist and constraint files
Found clock HW_BIST|SYSTEM_CLOCK with period 1000.00ns 
Found clock HW_BIST|FPGA_SYSTEMACE_CLOCK with period 1000.00ns 
Found clock HW_BIST|ac97_rst_sft_ps2_out[11] with period 1000.00ns 
Found clock HW_BIST|CLOCK_GEN.clk100_270_derived_clock with period 1000.00ns 
Found clock HW_BIST|CLOCK_GEN.clk100_90_derived_clock with period 1000.00ns 
Found clock HW_BIST|CLOCK_GEN.pix_clk_derived_clock with period 4000.00ns 
Found clock HW_BIST|CLOCK_GEN.clk100_180_derived_clock with period 1000.00ns 
Found clock HW_BIST|CLOCK_GEN.clk100_derived_clock with period 1000.00ns 
Found clock HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock with period 1000.00ns 
Found clock HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] with period 1000.00ns 
@W:"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\clock_gen.v":121:8:121:18|Net clk75_in appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\special_clk_div.v":51:0:51:5|Net shifter[15] appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\svga_timing_generation.v":181:0:181:5|Net N_193_iclk appears to be a clock source which was not identified. Assuming default frequency. 
@W:"c:\xup_v2pro_dev_brd\lib\xilinxprocessorip\pcores\hw_bist_v1_01_c\synplicity_build\onewire_master.v":438:5:438:6|Net crc appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 17 17:16:32 2005
#


Top view:               HW_BIST
Requested Frequency:    0.3 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..



Performance Summary 
*******************


Worst slack in design: 993.132

                                                                                       Requested     Estimated     Requested     Estimated                  Clock                                   Clock              
Starting Clock                                                                         Frequency     Frequency     Period        Period        Slack        Type                                    Group              
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
HW_BIST|CLOCK_GEN.clk100_derived_clock                                                 1.0 MHz       227.3 MHz     1000.000      4.399         995.601      derived (from HW_BIST|SYSTEM_CLOCK)     Inferred_clkgroup_0
HW_BIST|CLOCK_GEN.pix_clk_derived_clock                                                0.3 MHz       157.8 MHz     4000.000      6.335         3993.665     derived (from HW_BIST|SYSTEM_CLOCK)     Inferred_clkgroup_0
HW_BIST|FPGA_SYSTEMACE_CLOCK                                                           1.0 MHz       328.0 MHz     1000.000      3.049         996.951      inferred                                Inferred_clkgroup_1
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9]     1.0 MHz       192.1 MHz     1000.000      5.206         994.794      inferred                                Inferred_clkgroup_3
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock     1.0 MHz       284.9 MHz     1000.000      3.510         996.491      inferred                                Inferred_clkgroup_2
HW_BIST|ac97_rst_sft_ps2_out[11]                                                       1.0 MHz       227.3 MHz     1000.000      4.399         995.601      inferred                                Inferred_clkgroup_4
System                                                                                 1.0 MHz       145.6 MHz     1000.000      6.868         993.132      system                                  default_clkgroup   
=======================================================================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                                                                                  |    rise  to  rise      |    fall  to  fall     |    rise  to  fall   |    fall  to  rise 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                                            Ending                                                                              |  constraint  slack     |  constraint  slack    |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
HW_BIST|CLOCK_GEN.pix_clk_derived_clock                                             HW_BIST|CLOCK_GEN.pix_clk_derived_clock                                             |  4000.000    3993.665  |  No paths    -        |  No paths    -      |  No paths    -    
HW_BIST|CLOCK_GEN.clk100_derived_clock                                              HW_BIST|CLOCK_GEN.clk100_derived_clock                                              |  1000.000    995.601   |  No paths    -        |  No paths    -      |  No paths    -    
HW_BIST|ac97_rst_sft_ps2_out[11]                                                    HW_BIST|ac97_rst_sft_ps2_out[11]                                                    |  1000.000    995.601   |  No paths    -        |  No paths    -      |  No paths    -    
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9]  HW_BIST|CLOCK_GEN.pix_clk_derived_clock                                             |  No paths    -         |  Diff grp    -        |  No paths    -      |  No paths    -    
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9]  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9]  |  No paths    -         |  1000.000    994.794  |  No paths    -      |  No paths    -    
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9]  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock  |  No paths    -         |  No paths    -        |  No paths    -      |  Diff grp    -    
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock  HW_BIST|CLOCK_GEN.pix_clk_derived_clock                                             |  No paths    -         |  No paths    -        |  Diff grp    -      |  No paths    -    
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9]  |  No paths    -         |  No paths    -        |  Diff grp    -      |  No paths    -    
HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock  |  1000.000    996.491   |  No paths    -        |  No paths    -      |  No paths    -    
HW_BIST|FPGA_SYSTEMACE_CLOCK                                                        HW_BIST|FPGA_SYSTEMACE_CLOCK                                                        |  1000.000    996.951   |  No paths    -        |  No paths    -      |  No paths    -    
===================================================================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port                         Starting                                      User           Arrival     Required             
Name                         Reference                                     Constraint     Time        Time         Slack   
                             Clock                                                                                         
---------------------------------------------------------------------------------------------------------------------------
CPU_RESET                    System (rising)                               NA             0.000       1000.000     1000.000