hw_bist.plg

来自「Viertex 2 开发板的接口程序」· PLG 代码 · 共 43 行

@P:  Worst Slack : 993.132
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Estimated Frequency : 227.3 MHz
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Requested Frequency : 1.0 MHz
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Estimated Period : 4.399
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Requested Period : 1000.000
@P:  HW_BIST|CLOCK_GEN.clk100_derived_clock - Slack : 995.601
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Estimated Frequency : 157.8 MHz
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Requested Frequency : 0.3 MHz
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Estimated Period : 6.335
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Requested Period : 4000.000
@P:  HW_BIST|CLOCK_GEN.pix_clk_derived_clock - Slack : 3993.665
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Estimated Frequency : 328.0 MHz
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Requested Frequency : 1.0 MHz
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Estimated Period : 3.049
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Requested Period : 1000.000
@P:  HW_BIST|FPGA_SYSTEMACE_CLOCK - Slack : 996.951
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Estimated Frequency : 192.1 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Requested Frequency : 1.0 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Estimated Period : 5.206
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Requested Period : 1000.000
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.ONEWIRE_MASTER.jc2_q_inferred_clock[9] - Slack : 994.794
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Estimated Frequency : 284.9 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Requested Frequency : 1.0 MHz
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Estimated Period : 3.510
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Requested Period : 1000.000
@P:  HW_BIST|SILICON_SERIAL_NUMBER.ONEWIRE_IFACE.SPECIAL_CLK_DIVIDER.clk_inferred_clock - Slack : 996.491
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Estimated Frequency : 227.3 MHz
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Requested Frequency : 1.0 MHz
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Estimated Period : 4.399
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Requested Period : 1000.000
@P:  HW_BIST|ac97_rst_sft_ps2_out[11] - Slack : 995.601
@P:  System - Estimated Frequency : 145.6 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 6.868
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 993.132
@P: HW_BIST Part : xc2vp2fg256-7
@P: HW_BIST I/O primitives : 132
@P: HW_BIST I/O Register bits : 1
@P: HW_BIST Register bits (Non I/O) : 577 (20%)
@P: HW_BIST Block Rams : 17 of 12 (141%)
@P: HW_BIST Total Luts : 1356 (48%)