video_out.v

Viertex 2 开发板的接口程序

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//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : Video Output Mux
   Project    : XUP Virtex-II Pro Development System 
-------------------------------------------------------------------------------
   File       : VIDEO_OUT.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2005/06/15
   Copyright  : (c) Xilinx Inc, 2005
-------------------------------------------------------------------------------
   Uses       : 
-------------------------------------------------------------------------------
   Used by    : HW_BIST.v
-------------------------------------------------------------------------------
   Description: This module selects the correct video output data based on the
   				line count output of the video timing generator.
				The upper third of the display is character based data and will
				be displayed as white characters. The lower two thirds of the
				display is based on bit mapped data.
 
	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.


-------------------------------------------------------------------------------
*/
module VIDEO_OUT
(
pixel_clock,
reset,
VGA_OUT_PIXEL_CLOCK,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_COMP_SYNCH,
VGA_OUT_BLANK_Z,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE,
char_mode_data,
vga_red_bar_data,
vga_green_bar_data,
vga_blue_bar_data,
vga_ramp_data,
h_synch_delay,
v_synch_delay,
comp_synch,
blank,
line_count
);



input			pixel_clock;
input			reset;
output			VGA_OUT_PIXEL_CLOCK;
output			VGA_HSYNCH;
output			VGA_VSYNCH;
output			VGA_COMP_SYNCH;
output			VGA_OUT_BLANK_Z;
output	[7:0]	VGA_OUT_RED;
output	[7:0]	VGA_OUT_GREEN;
output	[7:0]	VGA_OUT_BLUE;
input	[7:0]	char_mode_data;
input	[7:0]	vga_red_bar_data;
input	[7:0]	vga_green_bar_data;
input	[7:0]	vga_blue_bar_data;
input	[7:0]	vga_ramp_data;
input			h_synch_delay;
input			v_synch_delay;
input			comp_synch;
input			blank;
input	[9:0]	line_count;

reg				VGA_HSYNCH;
reg				VGA_VSYNCH;
reg				VGA_COMP_SYNCH;
reg				VGA_OUT_BLANK_Z;
reg		[7:0]	VGA_OUT_RED;
reg		[7:0]	VGA_OUT_GREEN;
reg		[7:0]	VGA_OUT_BLUE;

wire high = 1'b1; 
wire low  = 1'b0; 

//wire VGA_OUT_PIXEL_CLOCK = pixel_clock;

// make the external video connections
always @ (posedge pixel_clock or posedge reset) begin
	if (reset) begin								// shut down the video output during reset
		VGA_HSYNCH	 		<= 1'b1;
		VGA_VSYNCH 	 		<= 1'b1;
		VGA_COMP_SYNCH 		<= 1'b1;
		VGA_OUT_BLANK_Z 	<= 1'b0;
		VGA_OUT_RED[7:0]	<= 8'h00;
		VGA_OUT_GREEN[7:0]	<= 8'h00;
		VGA_OUT_BLUE[7:0]	<= 8'h00;
		end
	else if (line_count < 160) begin				// display the character mode data
		VGA_HSYNCH	 		<= h_synch_delay;
		VGA_VSYNCH 	 		<= v_synch_delay;
		VGA_COMP_SYNCH 		<= 1'b0;		// disable sync on green
		VGA_OUT_BLANK_Z 	<= !blank;
		VGA_OUT_RED[7:0]	<= char_mode_data[7:0];	//silicon serial number and PS/2 data
		VGA_OUT_GREEN[7:0]	<= char_mode_data[7:0];
		VGA_OUT_BLUE[7:0]	<= char_mode_data[7:0];
		end
	else if ((line_count > 160) & (line_count < 318)) begin // color bars
		VGA_HSYNCH	 		<= h_synch_delay;
		VGA_VSYNCH 	 		<= v_synch_delay;
		VGA_COMP_SYNCH 		<= 1'b0;		// disable sync on green
		VGA_OUT_BLANK_Z 	<= !blank;
		VGA_OUT_RED[7:0]	<= vga_red_bar_data[7:0];
		VGA_OUT_GREEN[7:0]	<= vga_green_bar_data[7:0];
		VGA_OUT_BLUE[7:0]	<= vga_blue_bar_data[7:0];
		end
	else if (line_count > 320) begin				// black and white ramp
		VGA_HSYNCH	 		<= h_synch_delay;
		VGA_VSYNCH 	 		<= v_synch_delay;
		VGA_COMP_SYNCH 		<= 1'b0;		// disable sync on green
		VGA_OUT_BLANK_Z 	<= !blank;
		VGA_OUT_RED[7:0]	<= vga_ramp_data[7:0];
		VGA_OUT_GREEN[7:0]	<= vga_ramp_data[7:0];
		VGA_OUT_BLUE[7:0]	<= vga_ramp_data[7:0];
		end
	else begin										// default black screen
		VGA_HSYNCH	 		<= h_synch_delay;
		VGA_VSYNCH 	 		<= v_synch_delay;
		VGA_COMP_SYNCH 		<= 1'b0;		// disable sync on green
		VGA_OUT_BLANK_Z 	<= !blank;
		VGA_OUT_RED[7:0]	<= 8'h00;
		VGA_OUT_GREEN[7:0]	<= 8'h00;
		VGA_OUT_BLUE[7:0]	<= 8'h00;
		end
	end 

OFDDRTRSE  PIXEL_CLOCK_OUT(
.O   (VGA_OUT_PIXEL_CLOCK),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (low),
.D1  (high),
.R   (reset),
.S   (low),
.T   (low));


endmodule // VIDEO_OUT


 module OFDDRTRSE (O, C0, C1, CE, D0, D1, R, S, T); // synthesis syn_black_box
    output O;
    input  C0, C1, CE, D0, D1, R, S, T;
 endmodule