clock_gen.v

Viertex 2 开发板的接口程序

//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : CLOCK GENERATION & DISTRIBUTION
   Project    : XUP Virtex-II Pro Development System 
-------------------------------------------------------------------------------
   File       : CLOCK_GEN.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/12
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       : 
-------------------------------------------------------------------------------
   Used by    : HW_BIST.v
-------------------------------------------------------------------------------
   Description: This module interfaces to the various clocks on the 
		XUP Virtex-II Pro Development System and provides buffered clock
		outputs from the DCMs in addition to a global reset signal.

	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.


-------------------------------------------------------------------------------

*/

module CLOCK_GEN 
(
MGT_CLK_P,
MGT_CLK_N,
SYSTEM_CLOCK,
FPGA_SYSTEMACE_CLOCK,

_100MHz_clock,
_100_90_clock,
_100_180_clock,
_100_270_clock,
_75MHz_clock,
_32MHz_clock,
_25MHz_clock,
reset,
dcms_locked
);



input	MGT_CLK_P;				// 75MHz LVDS DIFFERENTIAL CLOCK FOR SATA
input	MGT_CLK_N;

input	SYSTEM_CLOCK;			// 100MHz LVTTL SYSTEM CLOCK
input	FPGA_SYSTEMACE_CLOCK;	// 32MHz SYSTEMACE CLOCK


output 	_100MHz_clock;			// buffered SYSTEM_CLOCK
output	_100_90_clock;
output	_100_180_clock;
output	_100_270_clock;
output 	_75MHz_clock;			// buffered MGT_CLK
output	_25MHz_clock;			// 1/3 * SYSTEM_CLOCK
output	_32MHz_clock;			// buffered FPGA_SYSTEMACE_CLOCK
output	reset;					// reset asserted when DCMs are NOT LOCKED
output  dcms_locked;
wire	low  = 1'b0;
wire	high = 1'b1;

wire	MGT_CLK_P;
wire	MGT_CLK_N;
wire	SYSTEM_CLOCK;
wire	FPGA_SYSTEMACE_CLOCK;

// signals associated with the system clock DCM
wire 	system_dcm_rst;
wire 	system_dcm_locked;
wire	_100MHz_clock;
wire	_100_90_clock;
wire	_100_180_clock;
wire	_100_170_clock;
wire	_25MHz_clock;
wire	clk100_in;
wire	clk100;
wire	pix_clk;


// signals associated with the systemACE DCM
wire 	sysace_dcm_rst;
wire 	systemace_dcm_locked;
wire	_32MHz_clock;
wire	clk32_in;
wire	clk32;

// signals associated with the MGT clock DCM
wire 	mgt_dcm_rst;
wire 	mgt_dcm_locked;
//wire	_75MHz_clock;
//wire    _300MHz_clock;
wire	clk75_in;
wire	clk75;
wire    clk75_X4;


// instantiate the differential clock input buffers
IBUFGDS MGT_CLK_BUF (
.O  (clk75_in),
.I  (MGT_CLK_P),
.IB (MGT_CLK_N)
);

IBUFG SYSTEM_CLOCK_BUF (
.O  (clk100_in),
.I  (SYSTEM_CLOCK)
);

IBUFG SYSTEMACE_CLOCK_BUF (
.O  (clk32_in),
.I  (FPGA_SYSTEMACE_CLOCK)
);

// instantiate the clock input buffers for the internal clocks
BUFG SYS_CLOCK_BUF (
.O  (_100MHz_clock),
.I  (clk100)
);

BUFG SYS_CLOCK_90_BUF (
.O  (_100_90_clock),
.I  (clk100_90)
);

BUFG SYS_CLOCK_180_BUF (
.O  (_100_180_clock),
.I  (clk100_180)
);

BUFG SYS_CLOCK_270_BUF (
.O  (_100_270_clock),
.I  (clk100_270)
);

BUFG MGT_CLOCK_BUF (
.O  (_75MHz_clock),
.I  (clk75)
);



BUFG SYSACE_CLOCK_BUF (
.O  (_32MHz_clock),
.I  (clk32_in)
);

BUFG PIXEL_CLOCK_BUF (
.O  (_25MHz_clock),
.I  (pix_clk)
);

assign dcms_locked = (system_dcm_locked & mgt_dcm_locked );

assign reset = !(system_dcm_locked & mgt_dcm_locked );

// instantiate the DCMs and DCM reset_in generation
DCM SYSTEM_DCM (
.CLKFB		(_100MHz_clock),
.CLKIN		(clk100_in),
.DSSEN		(low),
.PSCLK		(low),
.PSEN		(low),
.PSINCDEC	(low),
.RST		(system_dcm_rst),
.CLK0		(clk100),
.CLK90		(clk100_90),
.CLK180		(clk100_180),
.CLK270		(clk100_270),
.CLK2X		(),
.CLK2X180	(),
.CLKDV		(pix_clk),
.CLKFX		(),
.CLKFX180	(),
.LOCKED		(system_dcm_locked),
.PSDONE		(),
.STATUS		()
)
/* synthesis xc_props="DLL_FREQUENCY_MODE =LOW,DUTY_CYCLE_CORRECTION =TRUE,STARTUP_WAIT =FALSE,DFS_FREQUENCY_MODE =LOW,CLKFX_DIVIDE =1,CLKFX_MULTIPLY =3,CLKDV_DIVIDE =4,CLK_FEEDBACK =1X,CLKOUT_PHASE_SHIFT =NONE,PHASE_SHIFT =0"*/;


SRL16 RESET_SYSTEM_DCM (
.Q (system_dcm_rst),
.CLK (clk100_in),
.D (low),
.A0 (high),
.A1 (high),
.A2 (high),
.A3 (high)
)/*synthesis xc_props="INIT = 000F"*/;


DCM MGT_DCM (
.CLKFB		(_75MHz_clock),
.CLKIN		(clk75_in),
.DSSEN		(low),
.PSCLK		(low),
.PSEN		(low),
.PSINCDEC	(low),
.RST		(mgt_dcm_rst),
.CLK0		(clk75),
.CLK90		(),
.CLK180		(),
.CLK270		(),
.CLK2X		(),
.CLK2X180	(),
.CLKDV		(),
.CLKFX		(clk75_X4),
.CLKFX180	(),
.LOCKED		(mgt_dcm_locked),
.PSDONE		(),
.STATUS		()
)
/* synthesis xc_props="DLL_FREQUENCY_MODE =LOW,DUTY_CYCLE_CORRECTION =TRUE,STARTUP_WAIT =FALSE,DFS_FREQUENCY_MODE =LOW,CLKFX_DIVIDE =1,CLKFX_MULTIPLY =4, CLKDV_DIVIDE =2, CLK_FEEDBACK =1X,CLKOUT_PHASE_SHIFT =NONE,PHASE_SHIFT =0"*/;


SRL16 RESET_MGT_DCM (
.Q (mgt_dcm_rst),
.CLK (clk75_in),
.D (low),
.A0 (high),
.A1 (high),
.A2 (high),
.A3 (high)
)/*synthesis xc_props="INIT = 000F"*/;



endmodule //CLOCK_GEN