📄 onewire_master.v
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sr2_reset = 1'b0; // use sr2 to create a 480 us counter
NEXT_STATE = TX_RST_PLS;
end
end
/*
---------------------------------------
-- Detect Presence Pulse state
---------------------------------------
-- In this state, data on the one-wire
-- bus is sampled for the presence of a slave.
-- The data will be latched at 0~80 us.
-- Then it waits till total 500us has
-- has passed, and moves to next state
-- or goes back to INIT state according
-- to the presence of the "Presence
-- Pulse"
--
-- Use JC1 and SR2 here to count for
-- longer time duration (0 ~ 480 us):
--
-- Note:"Presence Pulse" indicates
-- a Serial Number Device is on the bus
-- and it's ready to operate.
----------------------------------------
*/
RX_PRE_PLS:begin
sr1_reset = 1'b1;
sr1_en = 1'b0;
sr2_reset = 1'b0; // use sr2 to create a 480 us counter
sr2_en = ts_60_to_80us; // enable sr2 to count every 80us
read_one_wire_dq = 1'b1;
data_to_one_wire_bus = 1'b0;
databyte_valid = 1'b0;
databit_valid = 1'b0;
if (sr2_q[6]) begin // wait for 480us to pass
if (data_from_one_wire_bus_pp == 1'b0 & data_from_one_wire_bus == 1'b1) begin // slave is present and pull-up is present
jc1_reset = 1'b1;
NEXT_STATE = TX_RD_CMD;
end
else begin // no slave present try again
jc1_reset = 1'b0;
NEXT_STATE = INIT;
end
end
else begin // 0 ~ 480 us
jc1_reset = 1'b0;
NEXT_STATE = RX_PRE_PLS;
end
end
/*
---------------------------------------
-- Transmit ROM Function Command state
---------------------------------------
-- In this state, the one-wire bus is
-- pulled down during first 10 us.
--
-- Then according to each bit of data
-- in the ROM Command (0x0F for Read ROM),
-- we write data to the Serial Number
-- Device:
-- (1) if we need to write '1' to the serial
-- number device, it will release
-- the one-wire bus to allow the
-- pull-up resistor to pull the wire to '1'.
-- (2) if we need to write '0' to
-- the device, we output '0' directly
-- to the bus. This process happens from
-- 10 us to 60 us.
--
-- After 60us, it releases the bus allowing
-- the one-wire bus to be pulled back to
-- high, and enable SR1 to shift to
-- next bit.
--
-- After another 20us, the transition of SR1
-- will take place. The process will repeat
-- to transmit another bit in the ROM Command,
-- till all 8 bits in the ROM Command have
-- been sent out.
--
-- After 8 bits of data has been sent out,
-- it moves to next state
-----------------------------------------
*/
TX_RD_CMD:begin
sr1_reset = 1'b0; // use sr1 to count the 8 bits in the read ROM command
sr2_reset = 1'b1;
sr2_en = 1'b0;
databyte_valid = 1'b0;
databit_valid = 1'b0;
if (ts_0_to_10us) begin // pull down one_wire bus
read_one_wire_dq = 1'b0;
data_to_one_wire_bus = 1'b0;
sr1_en = 1'b0;
jc1_reset = 1'b0;
NEXT_STATE = TX_RD_CMD;
end
else if (ts_60_to_80us) begin // release the bus
read_one_wire_dq = 1'b1;
data_to_one_wire_bus = 1'b1;
sr1_en = 1'b1; // bit has been sent enable the next bit
if (sr1_q[7]) begin // all command bits have been sent
jc1_reset = 1'b1;
NEXT_STATE = RX_DATA;
end
else begin // sent more bits
jc1_reset = 1'b0;
NEXT_STATE = TX_RD_CMD;
end
end
else begin // write the command bit from 10 us to 60 us
read_one_wire_dq = tx_cmd_bit;
data_to_one_wire_bus = tx_cmd_bit;
sr1_en = 1'b0;
jc1_reset = 1'b0;
NEXT_STATE = TX_RD_CMD; // send more read command bits
end
end
/*
---------------------------------------
-- Receive Serial Number Data state
---------------------------------------
-- In this state, the onewire bus is
-- pulled down during first 1 us, this
-- is the initialization of the Rx of one
-- bit . Then it release the bus by changing
-- back to read mode.
--
-- From 13us to 15 us, it samples the
-- data on the one-wire bus, and assert
-- databit_valid signal.
--
-- After 15us, it releases the bus allowing
-- the one-wire bus to be pulled back to
-- high.
--
-- At 60us, it enables SR1 to shift to
-- next bit. After 80us, one bit has
-- been read. Then it repeats
-- the process to receive other 7
-- bits in one byte.
--
-- After 8 bits for one byte of data have
-- been received, the SR2 is used to
-- count for total 8 bytes of serial
-- number data.
--
-- After 8 bytes of data has been received,
-- it moves to next state
-----------------------------------------
*/
RX_DATA:begin
sr1_reset = 1'b0; // start to use sr1 to count 8 bits.
// sr1 is configured to wrap around
// when it reach the end. So it's
// not necessary to reset it.
sr2_reset = 1'b0; // start to use sr2 to count the
// 8 bytes coming from the one-wire device
read_one_wire_dq = 1'b1;
data_to_one_wire_bus = 1'b1;
if (ts_0_to_1us) begin // pull down one_wire bus
read_one_wire_dq = 1'b0;
data_to_one_wire_bus = 1'b0;
databyte_valid = 1'b0;
databit_valid = 1'b0;
sr1_en = 1'b0;
sr2_en = 1'b0;
jc1_reset = 1'b0;
NEXT_STATE = RX_DATA;
end
else if (ts_60_to_80us) begin
read_one_wire_dq = 1'b1;
data_to_one_wire_bus = 1'b1;
databyte_valid = sr1_q[7]; // enable data output to external
// world when all 8 bits are read.
databit_valid = 1'b0;
sr1_en = 1'b1; // one bit has been read, enable the next bit
sr2_en = sr1_q[7]; // byte has been read, enable the next word
if (sr2_q[7] & databyte_valid) begin
jc1_reset = 1'b1;
NEXT_STATE = IDLE; // all 8 bytes have been received
end
else begin
jc1_reset = 1'b1;
NEXT_STATE = RX_DATA; // get more data
end
end
else begin // 1-60us
read_one_wire_dq = 1'b1; // release the bus
data_to_one_wire_bus = 1'b1;
databyte_valid = 1'b0;
databit_valid = ts_14_to_15us;
sr1_en = 1'b0;
sr2_en = 1'b0;
jc1_reset = 1'b0;
NEXT_STATE = RX_DATA; // continue to assemble the data bytes
end
end
/*
---------------------------------------
-- IDLE state
---------------------------------------
-- The onewire bus will be released to
-- read mode; the data bus will keep the
-- last byte (CRC value); crcok will
-- be valid as a latch signal.
--
-- Once enter IDLE state, it stays here
-- unless getting a system reset signal.
---------------------------------------
*/
IDLE:begin
sr1_reset = 1'b1;
sr1_en = 1'b0;
sr2_reset = 1'b1;
sr2_en = 1'b0;
read_one_wire_dq = 1'b1;
data_to_one_wire_bus = 1'b1;
databyte_valid = 1'b0;
databit_valid = 1'b0;
jc1_reset = 1'b0;
if (crc_ok) begin
NEXT_STATE = IDLE;
end
else begin
NEXT_STATE = INIT;
end
end
default:begin
sr1_reset = 1'b1;
sr1_en = 1'b0;
sr2_reset = 1'b1;
sr2_en = 1'b0;
read_one_wire_dq = 1'b1;
data_to_one_wire_bus = 1'b1;
databyte_valid = 1'b0;
databit_valid = 1'b0;
jc1_reset = 1'b0;
NEXT_STATE = INIT;
end
endcase
end
// capture the presence data if "0" then the slave is present otherwise the pullup is read
always @ (posedge ts_60_to_80us or posedge reset) begin
if (reset) begin
data_from_one_wire_bus_pp = 1'b1; // default to NOT present
end
else if (PRESENT_STATE == RX_PRE_PLS & sr2_q[0]) begin // first 60us slot
data_from_one_wire_bus_pp = data_from_one_wire_bus; // capture the presence bit
end
end
endmodule
module IOBUF(O, IO, I, T); // synthesis syn_black_box
output O;
inout IO;
input I;
input T;
endmodule
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