crcreg.v

Viertex 2 开发板的接口程序

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/*
-------------------------------------------------------------------------------
-- Title      : CRC Shift Register 
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : CRCreg.v
-- Company    : Xilinx Inc
-- Created    : 2001/03/15
-- Last update: 2001/03/15
-- Copyright  : (c) Xilinx Inc 1999, 2000
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_master.v
-------------------------------------------------------------------------------

-- Description: A parameterisable shift register to caculate crc
--              Suppose the data width is w, this CRCSR can handle
--              any CRC caculation based on following polynomia 
--              Polynomial = X^(w) + X^(f1) + X^(f2) + 1
--              where f1 and f2 are two feedbacks.
--              For example: Polynomial = x^8 + x^5 + x^4 + 1, which is
--              used for Dallas One-wire Serial Number device
--              Please refer to iButton standard at:
--              http://www.ibutton.com/ibuttons/standard.pdf
-------------------------------------------------------------------------------
*/


module CRCReg (clk,reset,en,din,q);
input clk;
input reset;
input en;
input din;
output [7:0] q;

reg [7:0] q;

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[0] <=1'b0;
		end
	else if (en) begin
		q[0] <= q[1];
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[1] <=1'b0;
		end
	else if (en) begin
		q[1] <= q[2];
		end
	end


always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[2] <=1'b0;
		end
	else if (en) begin
		q[2] <= ((din ^ q[0]) ^ q[3]);
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[3] <=1'b0;
		end
	else if (en) begin
		q[3] <= ((din ^ q[0]) ^ q[4]);
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[4] <=1'b0;
		end
	else if (en) begin
		q[4] <= q[5];
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[5] <=1'b0;
		end
	else if (en) begin
		q[5] <= q[6];
		end
	end


always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[6] <=1'b0;
		end
	else if (en) begin
		q[6] <= q[7];
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[7] <=1'b0;
		end
	else if (en) begin
		q[7] <= (din ^ q[0]);
		end
	end

endmodule