video_out_all_ddr.v

Viertex 2 开发板的接口程序

//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : Video Output Mux
   Project    : XUP Virtex-II Pro Development System
-------------------------------------------------------------------------------
   File       : VIDEO_OUT.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/12
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       :
-------------------------------------------------------------------------------
   Used by    : HW_BIST.v
-------------------------------------------------------------------------------
   Description: This module selects the correct video output data based on the
                                line count output of the video timing generator.
                                The upper third of the display is character based data and will
                                be displayed as white characters. The lower two thirds of the
                                display is based on bit mapped data.

        Conventions:
                All external port signals are UPPER CASE.
                All internal signals are LOWER CASE and are active HIGH.


-------------------------------------------------------------------------------
*/
module VIDEO_OUT
(
pixel_clock,
reset,
VGA_OUT_PIXEL_CLOCK,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_COMP_SYNCH,
VGA_OUT_BLANK_Z,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE,
char_mode_data,
vga_red_bar_data,
vga_green_bar_data,
vga_blue_bar_data,
vga_ramp_data,
h_synch_delay,
v_synch_delay,
comp_synch,
blank,
line_count,
vga_out_ena_n
);



input                   pixel_clock;
input                   reset;
output                  VGA_OUT_PIXEL_CLOCK;
output                  VGA_HSYNCH;
output                  VGA_VSYNCH;
output                  VGA_COMP_SYNCH;
output                  VGA_OUT_BLANK_Z;
output  [7:0]   VGA_OUT_RED;
output  [7:0]   VGA_OUT_GREEN;
output  [7:0]   VGA_OUT_BLUE;
input   [7:0]   char_mode_data;
input   [7:0]   vga_red_bar_data;
input   [7:0]   vga_green_bar_data;
input   [7:0]   vga_blue_bar_data;
input   [7:0]   vga_ramp_data;
input                   h_synch_delay;
input                   v_synch_delay;
input                   comp_synch;
input                   blank;
input   [9:0]   line_count;
input           vga_out_ena_n;

reg                     vga_hsynch_i;
reg                    vga_vsynch_i;
reg                     vga_comp_synch_i;
reg                    vga_out_blank_z_i;
reg            [7:0]   vga_out_red_i;
reg             [7:0]   vga_out_green_i;
reg             [7:0]   vga_out_blue_i;
wire                    high;
wire                     low;



assign high = 1'b1;
assign low = 1'b0;

// make the external video connections
always @ (posedge pixel_clock or posedge reset) begin
//always @ *
        if (reset) begin                                                        // shut down the video output during reset
                vga_hsynch_i              <= 1'b1;
                vga_vsynch_i              <= 1'b1;
                vga_comp_synch_i          <= 1'b1;
                vga_out_blank_z_i         <= 1'b0;
                vga_out_red_i[7:0]        <= 8'h00;
                vga_out_green_i[7:0]      <= 8'h00;
                vga_out_blue_i[7:0]       <= 8'h00;
                end
        else if (line_count < 160) begin                                // display the character mode data
                vga_hsynch_i             <= !h_synch_delay;
                vga_vsynch_i             <= !v_synch_delay;
                vga_comp_synch_i         <= !comp_synch;
                vga_out_blank_z_i         <= !blank;
                vga_out_red_i[7:0]        <= char_mode_data[7:0]; //silicon serial number and PS/2 data
                vga_out_green_i[7:0]      <= char_mode_data[7:0];
                vga_out_blue_i[7:0]       <= char_mode_data[7:0];
                end
        else if ((line_count > 160) & (line_count < 318)) begin // color bars
                vga_hsynch_i              <= !h_synch_delay;
                vga_vsynch_i              <= !v_synch_delay;
                vga_comp_synch_i          <= !comp_synch;
                vga_out_blank_z_i         <= !blank;
                vga_out_red_i[7:0]        <= vga_red_bar_data[7:0];
                vga_out_green_i[7:0]      <= vga_green_bar_data[7:0];
                vga_out_blue_i[7:0]       <= vga_blue_bar_data[7:0];
                end
        else if (line_count > 320) begin                                // black and white ramp
                vga_hsynch_i              <= !h_synch_delay;
                vga_vsynch_i              <= !v_synch_delay;
                vga_comp_synch_i          <= !comp_synch;
                vga_out_blank_z_i         <= !blank;
                vga_out_red_i[7:0]        <= vga_ramp_data[7:0];
                vga_out_green_i[7:0]      <= vga_ramp_data[7:0];
                vga_out_blue_i[7:0]       <= vga_ramp_data[7:0];
                end
        else begin                                                                              // default black screen
                vga_hsynch_i              <= !h_synch_delay;
                vga_vsynch_i              <= !v_synch_delay;
                vga_comp_synch_i          <= !comp_synch;
                vga_out_blank_z_i         <= !blank;
                vga_out_red_i[7:0]        <= 8'h00;
                vga_out_green_i[7:0]      <= 8'h00;
                vga_out_blue_i[7:0]       <= 8'h00;
                end
     end


OFDDRTRSE RED_0 (
.O   (VGA_OUT_RED[0]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[0]),
.D1  (vga_out_red_i[0]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_1 (
.O   (VGA_OUT_RED[1]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[1]),
.D1  (vga_out_red_i[1]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_2 (
.O   (VGA_OUT_RED[2]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[2]),
.D1  (vga_out_red_i[2]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_3 (
.O   (VGA_OUT_RED[3]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[3]),
.D1  (vga_out_red_i[3]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_4 (
.O   (VGA_OUT_RED[4]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[4]),
.D1  (vga_out_red_i[4]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_5 (
.O   (VGA_OUT_RED[5]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[5]),
.D1  (vga_out_red_i[5]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_6 (
.O   (VGA_OUT_RED[6]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[6]),
.D1  (vga_out_red_i[6]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE RED_7 (
.O   (VGA_OUT_RED[7]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_red_i[7]),
.D1  (vga_out_red_i[7]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_0 (
.O   (VGA_OUT_GREEN[0]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[0]),
.D1  (vga_out_green_i[0]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_1 (
.O   (VGA_OUT_GREEN[1]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[1]),
.D1  (vga_out_green_i[1]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_2 (
.O   (VGA_OUT_GREEN[2]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[2]),
.D1  (vga_out_green_i[2]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_3 (
.O   (VGA_OUT_GREEN[3]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[3]),
.D1  (vga_out_green_i[3]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);
OFDDRTRSE GREEN_4 (
.O   (VGA_OUT_GREEN[4]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[4]),
.D1  (vga_out_green_i[4]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_5 (
.O   (VGA_OUT_GREEN[5]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[5]),
.D1  (vga_out_green_i[5]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_6 (
.O   (VGA_OUT_GREEN[6]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[6]),
.D1  (vga_out_green_i[6]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE GREEN_7 (
.O   (VGA_OUT_GREEN[7]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_green_i[7]),
.D1  (vga_out_green_i[7]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE BLUE_0 (
.O   (VGA_OUT_BLUE[0]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[0]),
.D1  (vga_out_blue_i[0]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n));

OFDDRTRSE BLUE_1 (
.O   (VGA_OUT_BLUE[1]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[1]),
.D1  (vga_out_blue_i[1]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE BLUE_2 (
.O   (VGA_OUT_BLUE[2]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[2]),
.D1  (vga_out_blue_i[2]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n));

OFDDRTRSE BLUE_3 (
.O   (VGA_OUT_BLUE[3]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[3]),
.D1  (vga_out_blue_i[3]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE BLUE_4 (
.O   (VGA_OUT_BLUE[4]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[4]),
.D1  (vga_out_blue_i[4]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE BLUE_5 (
.O   (VGA_OUT_BLUE[5]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[5]),
.D1  (vga_out_blue_i[5]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE BLUE_6 (
.O   (VGA_OUT_BLUE[6]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[6]),
.D1  (vga_out_blue_i[6]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE BLUE_7 (
.O   (VGA_OUT_BLUE[7]),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blue_i[7]),
.D1  (vga_out_blue_i[7]),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n));

OFDDRTRSE HSYNC (
.O   (VGA_HSYNCH),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_hsynch_i),
.D1  (vga_hsynch_i),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE VSYNC (
.O   (VGA_VSYNCH),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_vsynch_i),
.D1  (vga_vsynch_i),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE  COMP_SYNC(
.O   (VGA_COMP_SYNCH),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_comp_synch_i),
.D1  (vga_comp_synch_i),
.R   (low),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE  BLANK(
.O   (VGA_OUT_BLANK_Z),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (vga_out_blank_z_i),
.D1  (vga_out_blank_z_i),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n)
);

OFDDRTRSE  PIXEL_CLOCK(
.O   (VGA_OUT_PIXEL_CLOCK),
.C0  (pixel_clock),
.C1  (!pixel_clock),
.CE  (high),
.D0  (low),
.D1  (high),
.R   (reset),
.S   (low),
.T   (vga_out_ena_n));


endmodule // VIDEO_OUT


 module OFDDRTRSE (O, C0, C1, CE, D0, D1, R, S, T); // synthesis syn_black_box
    output O;
    input  C0, C1, CE, D0, D1, R, S, T;
 endmodule