expansion_ports.v

Viertex 2 开发板的接口程序

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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : EXPANSION PORT TEST
   Project    : XUP Virtex-II Pro Development System
-------------------------------------------------------------------------------

   File       : EXPANSION_PORTS.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/12
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       : 
-------------------------------------------------------------------------------
   Used by    : HW_BIST.v
-------------------------------------------------------------------------------
    Description: 	This design creates a walking one across the expansion ports.
					There should be a ~20nS pulse every 1.6uS


	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.

-------------------------------------------------------------------------------
*/

module  EXPANSION_PORT_TEST
(
_100MHz_clock,
reset,
hw_test_enable,
sft_test_enable,
sft_test_data,
sft_test_clk,
sft_test_rd_data_lo,
sft_test_rd_data_hi,
EXPANSION_PORT,
HIGH_SPEED_PORT
);

input	_100MHz_clock;			// 100MHz LVTTL SYSTEM CLOCK
input	reset;
input	hw_test_enable;
input	sft_test_enable;
input	sft_test_data;
input	sft_test_clk;
output [0:31] sft_test_rd_data_lo;
output [0:31] sft_test_rd_data_hi;
output [79:0] EXPANSION_PORT;	// header pins and low-speed Digilent port
output [42:0] HIGH_SPEED_PORT;	// high-speed Digilent port


reg [79:0] counter0;
reg [52:0] counter1;

reg _50mhz_clock;
wire oe_hw_test;
wire [52:0] mux_out;
wire [52:0] oe_enable_dual;

assign oe_hw_test = !(hw_test_enable);
assign sft_test_rd_data_hi[0:10] = 11'b0;   // tie unused read bits to zero

// create a 50MHz clock
always @ (posedge _100MHz_clock or posedge reset) begin
	if (reset) begin
		_50mhz_clock <= 1'b0;
		end
	else begin
		_50mhz_clock <= ~_50mhz_clock;
		end
	end

// create the walking one test pattern
always @ (posedge _100MHz_clock or posedge reset) begin
	if (reset) begin
		counter0[79:0] <= 80'h00000001;
		end
	else if (_50mhz_clock) begin
		counter0[79:1] <= counter0[78:0];
		counter0[0] <= counter0[79];
		end
	end


    // create the software controlled walking one test pattern
always @ (posedge sft_test_clk or posedge reset) begin
	if (reset) begin
		counter1[52:0] <= 53'b0;
		end
	else  begin
		counter1[52:0] <= {counter1[51:0] , sft_test_data}  ;
		end
	end

//assign EXPANSION_PORT[79:0] = counter0[79:0];
//assign HIGH_SPEED_PORT[42:0] = counter0[42:0];

// expansion pins only driven by hardware test no read
IOBUF expan_port_0(.O(), .IO(EXPANSION_PORT[0]), .I(counter0[0]), .T(oe_hw_test)); 
IOBUF expan_port_1(.O(), .IO(EXPANSION_PORT[1]), .I(counter0[1]), .T(oe_hw_test)); 
IOBUF expan_port_2(.O(), .IO(EXPANSION_PORT[2]), .I(counter0[2]), .T(oe_hw_test)); 
IOBUF expan_port_3(.O(), .IO(EXPANSION_PORT[3]), .I(counter0[3]), .T(oe_hw_test)); 
IOBUF expan_port_4(.O(), .IO(EXPANSION_PORT[4]), .I(counter0[4]), .T(oe_hw_test)); 
IOBUF expan_port_5(.O(), .IO(EXPANSION_PORT[5]), .I(counter0[5]), .T(oe_hw_test)); 
IOBUF expan_port_6(.O(), .IO(EXPANSION_PORT[6]), .I(counter0[6]), .T(oe_hw_test)); 
IOBUF expan_port_7(.O(), .IO(EXPANSION_PORT[7]), .I(counter0[7]), .T(oe_hw_test)); 
IOBUF expan_port_40(.O(), .IO(EXPANSION_PORT[40]), .I(counter0[40]), .T(oe_hw_test)); 
IOBUF expan_port_41(.O(), .IO(EXPANSION_PORT[41]), .I(counter0[41]), .T(oe_hw_test)); 
IOBUF expan_port_42(.O(), .IO(EXPANSION_PORT[42]), .I(counter0[42]), .T(oe_hw_test)); 
IOBUF expan_port_43(.O(), .IO(EXPANSION_PORT[43]), .I(counter0[43]), .T(oe_hw_test));
IOBUF expan_port_44(.O(), .IO(EXPANSION_PORT[44]), .I(counter0[44]), .T(oe_hw_test));
IOBUF expan_port_77(.O(), .IO(EXPANSION_PORT[77]), .I(counter0[77]), .T(oe_hw_test));
IOBUF expan_port_78(.O(), .IO(EXPANSION_PORT[78]), .I(counter0[78]), .T(oe_hw_test));
IOBUF expan_port_79(.O(), .IO(EXPANSION_PORT[79]), .I(counter0[79]), .T(oe_hw_test));
IOBUF hs_expan_42(.O(), .IO(HIGH_SPEED_PORT[42]), .I(counter0[42]), .T(oe_hw_test));

 
// expansion pins  driven by both  hardware and software test
assign mux_out[0] = hw_test_enable ? counter0[8] : counter1[0];
assign oe_enable_dual[0] = !(counter1[0] | hw_test_enable);
IOBUF expan_port_8(.O(), .IO(EXPANSION_PORT[8]), .I(mux_out[0]), .T(oe_enable_dual[0]));
assign mux_out[1] = hw_test_enable ? counter0[9] : counter1[1];
assign oe_enable_dual[1] = !(counter1[1] | hw_test_enable);
IOBUF expan_port_9(.O(), .IO(EXPANSION_PORT[9]), .I(mux_out[1]), .T(oe_enable_dual[1]));
assign mux_out[2] = hw_test_enable ? counter0[11] : counter1[2];
assign oe_enable_dual[2] = !(counter1[2] | hw_test_enable);
IOBUF expan_port_11(.O(), .IO(EXPANSION_PORT[11]), .I(mux_out[2]), .T(oe_enable_dual[2]));
assign mux_out[3] = hw_test_enable ? counter0[13] : counter1[3];
assign oe_enable_dual[3] = !(counter1[3] | hw_test_enable);
IOBUF expan_port_13(.O(), .IO(EXPANSION_PORT[13]), .I(mux_out[3]), .T(oe_enable_dual[3]));
assign mux_out[4] = hw_test_enable ? counter0[15] : counter1[4];
assign oe_enable_dual[4] = !(counter1[4] | hw_test_enable);
IOBUF expan_port_15(.O(), .IO(EXPANSION_PORT[15]), .I(mux_out[4]), .T(oe_enable_dual[4]));
assign mux_out[5] = hw_test_enable ? counter0[17] : counter1[5];
assign oe_enable_dual[5] = !(counter1[5] | hw_test_enable);
IOBUF expan_port_17(.O(), .IO(EXPANSION_PORT[17]), .I(mux_out[5]), .T(oe_enable_dual[5]));
assign mux_out[6] = hw_test_enable ? counter0[19] : counter1[6];
assign oe_enable_dual[6] = !(counter1[6] | hw_test_enable);
IOBUF expan_port_19(.O(), .IO(EXPANSION_PORT[19]), .I(mux_out[6]), .T(oe_enable_dual[6]));
assign mux_out[7] = hw_test_enable ? counter0[21] : counter1[7];
assign oe_enable_dual[7] = !(counter1[7] | hw_test_enable);
IOBUF expan_port_21(.O(), .IO(EXPANSION_PORT[21]), .I(mux_out[7]), .T(oe_enable_dual[7]));
assign mux_out[8] = hw_test_enable ? counter0[23] : counter1[8];
assign oe_enable_dual[8] = !(counter1[8] | hw_test_enable);
IOBUF expan_port_23(.O(), .IO(EXPANSION_PORT[23]), .I(mux_out[8]), .T(oe_enable_dual[8]));
assign mux_out[9] = hw_test_enable ? counter0[25] : counter1[9];
assign oe_enable_dual[9] = !(counter1[9] | hw_test_enable);
IOBUF expan_port_25(.O(), .IO(EXPANSION_PORT[25]), .I(mux_out[9]), .T(oe_enable_dual[9]));
assign mux_out[10] = hw_test_enable ? counter0[27] : counter1[10];
assign oe_enable_dual[10] = !(counter1[10] | hw_test_enable);
IOBUF expan_port_27(.O(), .IO(EXPANSION_PORT[27]), .I(mux_out[10]), .T(oe_enable_dual[10]));
assign mux_out[11] = hw_test_enable ? counter0[29] : counter1[11];
assign oe_enable_dual[11] = !(counter1[11] | hw_test_enable);
IOBUF expan_port_29(.O(), .IO(EXPANSION_PORT[29]), .I(mux_out[11]), .T(oe_enable_dual[11]));
assign mux_out[12] = hw_test_enable ? counter0[31] : counter1[12];
assign oe_enable_dual[12] = !(counter1[12] | hw_test_enable);
IOBUF expan_port_31(.O(), .IO(EXPANSION_PORT[31]), .I(mux_out[12]), .T(oe_enable_dual[12]));
assign mux_out[13] = hw_test_enable ? counter0[33] : counter1[13];
assign oe_enable_dual[13] = !(counter1[13] | hw_test_enable);
IOBUF expan_port_33(.O(), .IO(EXPANSION_PORT[33]), .I(mux_out[13]), .T(oe_enable_dual[13]));
assign mux_out[14] = hw_test_enable ? counter0[35] : counter1[14];