parallel_sn_data.v

Viertex 2 开发板的接口程序

//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
-- Title      : parallel output serial number data register
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : parallel_sn_data.v
-- Company    : Xilinx, Inc.
-- Created    : 2001/03/15
-- Last Update: 2001/03/15
-- Copyright  : (c) Xilinx Inc, 2001
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_master.v
-------------------------------------------------------------------------------
-- Description: This module creates the parallel 48 bit data register for the
--				serial number read from the one-wire device.
--
-------------------------------------------------------------------------------

*/
module PARALLEL_SN_DATA (clk, reset, data, enable, sn_data); 
input 			clk;
input 			reset;
input	[7:0]	data;
input 	[5:0] 	enable;
output 	[47:0]	sn_data;

reg		[47:0] sn_data;

always @ (posedge clk or posedge reset) begin
 	if (reset) begin
		sn_data[7:0] <= 8'h00;
		end
	else if (enable[0]) begin					// latch the first byte
		sn_data[7:0] <= data[7:0];
		end
	end

always @ (posedge clk or posedge reset) begin
 	if (reset) begin
		sn_data[15:8] <= 8'h00;
		end
	else if (enable[1]) begin					// latch the second byte
		sn_data[15:8] <= data[7:0];
		end
	end

always @ (posedge clk or posedge reset) begin
 	if (reset) begin
		sn_data[23:16] <= 8'h00;
		end
	else if (enable[2]) begin					// latch the third byte
		sn_data[23:16] <= data[7:0];
		end
	end

always @ (posedge clk or posedge reset) begin
 	if (reset) begin
		sn_data[31:24] <= 8'h00;
		end
	else if (enable[3]) begin					// latch the fourth byte
		sn_data[31:24] <= data[7:0];
		end
	end
always @ (posedge clk or posedge reset) begin
 	if (reset) begin
		sn_data[39:32] <= 8'h00;
		end
	else if (enable[4]) begin					// latch the fifth byte
		sn_data[39:32] <= data[7:0];
		end
	end

always @ (posedge clk or posedge reset) begin
 	if (reset) begin
		sn_data[47:40] <= 8'h00;
		end
	else if (enable[5]) begin					// latch the sixth byte
		sn_data[47:40] <= data[7:0];
		end
	end

endmodule