video_ram.v

Viertex 2 开发板的接口程序

//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : SVGA bit mapped video data  RAM
   Project    : XUP Virtex-II Pro Development System
-------------------------------------------------------------------------------
   File       : VIDEO_RAM.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/12
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       : 
-------------------------------------------------------------------------------
   Used by    : 
-------------------------------------------------------------------------------
   Description: This module creates a 8K x 8 RAM that is used as the video
				data RAM.

   Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.


-------------------------------------------------------------------------------
*/
module VIDEO_RAM (
read_clk,
read_data,
read_addr,
read_enable,
write_data,
write_addr,
write_clk,
write_enable
);

input		read_clk;
output [7:0]read_data;
input [12:0]read_addr;
input		read_enable;

input [7:0] write_data;
input [12:0]write_addr;
input		write_clk;
input		write_enable;

wire 		read_clk;
wire [7:0] 	read_data;
wire [12:0] read_addr;
wire 		read_enable;

wire 		write_clock;
wire [7:0] 	write_data;
wire [12:0] write_addr;
wire 		write_enable;


// instantiate the RAMs

RAMB16_S2_S2 RAM_BITS_1_0 (
.DOA(),
.ADDRA(write_addr[12:0]),
.CLKA(write_clk),
.DIA(write_data[1:0]),
.ENA(write_enable),
.WEA(1'b1),
.SSRA(1'b0),

.DOB(read_data[1:0]),
.ADDRB(read_addr[12:0]),
.CLKB(read_clk),
.DIB(2'b00),
.ENB(read_enable),
.WEB(1'b0),
.SSRB(1'b0)
);

RAMB16_S2_S2 RAM_BITS_3_2 (
.DOA(),
.ADDRA(write_addr[12:0]),
.CLKA(write_clk),
.DIA(write_data[3:2]),
.ENA(write_enable),
.WEA(1'b1),
.SSRA(1'b0),

.DOB(read_data[3:2]),
.ADDRB(read_addr[12:0]),
.CLKB(read_clk),
.DIB(2'b00),
.ENB(read_enable),
.WEB(1'b0),
.SSRB(1'b0)
);

RAMB16_S2_S2 RAM_BITS_5_4 (
.DOA(),
.ADDRA(write_addr[12:0]),
.CLKA(write_clk),
.DIA(write_data[5:4]),
.ENA(write_enable),
.WEA(1'b1),
.SSRA(1'b0),

.DOB(read_data[5:4]),
.ADDRB(read_addr[12:0]),
.CLKB(read_clk),
.DIB(2'b00),
.ENB(read_enable),
.WEB(1'b0),
.SSRB(1'b0)
);

RAMB16_S2_S2 RAM_BITS_7_6 (
.DOA(),
.ADDRA(write_addr[12:0]),
.CLKA(write_clk),
.DIA(write_data[7:6]),
.ENA(write_enable),
.WEA(1'b1),
.SSRA(1'b0),

.DOB(read_data[7:6]),
.ADDRB(read_addr[12:0]),
.CLKB(read_clk),
.DIB(2'b00),
.ENB(read_enable),
.WEB(1'b0),
.SSRB(1'b0)
);

// synthesis translate_off
// clear the memories 
defparam RAM_BITS_1_0 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAM_BITS_1_0 .INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

defparam RAM_BITS_1_0 .INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
    
defparam RAM_BITS_1_0 .INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam RAM_BITS_1_0 .INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;