onewire_iface.v

Viertex 2 开发板的接口程序

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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
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/*

-------------------------------------------------------------------------------
-- Title      : An interface to use 1-Wire(TM) Master
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : ONEWIRE_IFACE.v
-- Company    : Xilinx, Inc.
-- Created    : 2001/03/15
-- Last Update: 2001/03/15
-- Copyright  : (c) Xilinx Inc, 2001
-------------------------------------------------------------------------------
-- Uses       : ONEWIRE_MASTER.v, SPECIAL_CLK_DIVIDER.v, defines.v
-------------------------------------------------------------------------------
-- Used by    : Any user system connecting to a 1-Wire device
-------------------------------------------------------------------------------
-- Description: An interface to show how to use the 1-Wire Master
--
--              It will output the data from the DS2401 byte by byte
--              while data_valid is asserted. Totally 8 bytes of data will
--              show up on the data bus in sequence of:
--                Family code (x01 for DS2401) : 1 byte
--                Serial number (e.g. xABCDEF) : 6 bytes
--                CRC value (based on polynomial=X^8 + X^5 + X^4 + 1) : 1 byte
--              So, user will get total 8 strobes of data_valid after the reset.
--                
--              It connects to the DS2401 through only one wire (sndq),
--              which is a bidirectional data path with internal pullup
--              resistor (about 13K Ohm, which is higher than the specification
--              of 5K Ohm on the DS2401 datasheet).
--
--              It uses a clock divider to generate a slow clock (1MHz) for
--              the 1-Wire Master module from the system clock. Use a generic
--              (CLK_DIV) to specify the divider ratio for different input
--              clock rate.
--
--              It generates a crc_ok signal which indicates all the data have
--              been received/output and crc checking is OK if the parameter
--              CheckCRC is defined.
--              
-------------------------------------------------------------------------------
*/

`include "defines.v"

module ONEWIRE_IFACE (sys_clk, sys_reset, dq, data, data_valid, crc_ok, sn_data);
input 			sys_clk; 		// system clock
input 			sys_reset; 		// active high reset
inout 			dq;				// one wire interface
output [7:0] 	data;			// received data byte
output 			data_valid;		// data output valid 20us strobe
output 			crc_ok;			// crc ok active high
output [47:0]	sn_data;		// paralled sn data

wire [7:0] 	data;
wire [47:0] sn_data;
wire 		data_valid;
wire 		crc_ok;
wire 		dq;

wire reset;
wire sys_clk;
wire clk_1MHz;

assign reset = sys_reset;

/*
// instantiate the clock divider module
CLK_DIVIDER CLK_DIVIDER (
.reset(reset),
.clk_in(sys_clk),
.clk_out(clk_1MHz)
);
*/
// instantiate the clock divider module
SPECIAL_CLK_DIVIDER SPECIAL_CLK_DIVIDER (
.reset(reset),
.clk_in(sys_clk),
.clk_out(clk_1MHz)
);

// instantiate the one wire master module
ONEWIRE_MASTER  ONEWIRE_MASTER(
.clk(clk_1MHz), 
.reset(reset), 
.dq(dq), 
.data_out(data[7:0]), 
.data_valid(data_valid), 
.crc_ok(crc_ok),
.sn_data(sn_data[47:0]),
.sys_clk(sys_clk)
);

// instantiate the INTERNAL pullup for the one wire interface if required
`ifdef  UsePULLUP

PULLUP PULLUP (
.O(dq)
);
`else
`endif

endmodule

`ifdef  UsePULLUP
module PULLUP(O); /* synthesis syn_black_box .noprune=1 */
output O /* synthesis syn_not_a_driver=1 */;
endmodule
`else
`endif