character_mode.v

Viertex 2 开发板的接口程序

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//     (c) Copyright 2003 Xilinx, Inc.
//     All rights reserved.
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/*
-------------------------------------------------------------------------------
   Title      : SVGA Video Output Character Mode Data Serializer
   Project    : XUP Virtex-II Pro Development System
-------------------------------------------------------------------------------
   File       : CHARACTER_MODE.v
   Company    : Xilinx, Inc.
   Created    : 2001/07/17
   Last Update: 2001/07/17
   Copyright  : (c) Xilinx Inc, 2001
-------------------------------------------------------------------------------
   Uses       : CHAR_RAM.v CHAR_GEN_ROM.v
-------------------------------------------------------------------------------
   Used by    : CHAR_MODE.v
-------------------------------------------------------------------------------
   Description: This module is used to create the serial pixel data for the character 
		mode svga display. The pixel data is common to all eight bits to be
		displayed as bright white.

	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.

-------------------------------------------------------------------------------
*/

module CHARACTER_MODE(
// write side
char_write_addr,
char_write_data,
char_write_enable,
char_write_clock,

// read side
char_address,
char_line_count,
char_pixel,
pixel_clock,
char_mode_data,

// control
reset
);

input			pixel_clock;
input			reset;
input [2:0]  	char_line_count;// line number within 8 line block
input [12:0] 	char_address;	// character address "0" is upper left character
input [2:0]  	char_pixel;		// pixel position within 8 pixel block
output [7:0]	char_mode_data;
input [12:0]   	char_write_addr;
input [7:0] 	char_write_data;
input			char_write_enable;
input 			char_write_clock;

reg [7:0] 		char_mode_data;
reg 			latch_data;
reg 			latch_low_data;
reg 			shift_high;
reg 			shift_low;
reg [3:0] 		latched_low_char_data;
reg [7:0] 		latched_char_data;
wire [7:0] 		character_data;
wire [7:0] 		char_gen_rom_data;
reg 			char_pix;
wire [7:0] 		ascii_code;
wire [2:0] 		char_line_count;
wire [12:0] 	char_addr;
wire [12:0] 	char_write_addr;
wire [7:0] 		char_write_data;
wire 			char_write_enable;
wire 			char_write_clock;
wire [10:0] 	chargen_rom_address;
wire [12:0] 	char_address;		

 
// instantiate the CHARACTER MODE DISPLAY RAM

CHAR_RAM CHAR_RAM(
.read_clk(pixel_clock),
.read_data(ascii_code[7:0]),
.read_addr(char_address[12:0]),
.read_enable(1'b1),
.write_data(char_write_data[7:0]),
.write_addr(char_write_addr),
.write_clk(char_write_clock),
.write_enable(char_write_enable)
);


// instantiate the character generator ROM


CHAR_GEN_ROM CHAR_GEN_ROM(
.pixel_clock(pixel_clock),
.address(chargen_rom_address),
.data(char_gen_rom_data[7:0])
);

assign chargen_rom_address = {ascii_code[7:0],char_line_count[2:0]};


// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM
always @ (posedge pixel_clock or posedge reset)begin
			if (reset) begin
				latch_data <= 1'b0;
				end
			else if (char_pixel == 3'b110) begin
				latch_data <= 1'b1;
				end
			else if (char_pixel == 3'b111) begin
				latch_data <= 1'b0;
				end
			end

always @ (posedge pixel_clock or posedge reset)begin
			if (reset) begin
				latch_low_data <= 1'b0;
				end
			else if (char_pixel == 3'b010) begin
				latch_low_data <= 1'b1;
				end
			else if (char_pixel == 3'b011) begin
				latch_low_data <= 1'b0;
				end
			end

always @ (posedge pixel_clock or posedge reset)begin
			if (reset) begin
				shift_high <= 1'b1;
				end
			else if (char_pixel == 3'b011) begin
				shift_high <= 1'b0;
				end
			else if (char_pixel == 3'b111) begin
				shift_high <= 1'b1;
				end
			end

always @ (posedge pixel_clock or posedge reset)begin
			if (reset) begin
				shift_low <= 1'b0;
				end
			else if (char_pixel == 3'b011) begin
				shift_low <= 1'b1;
				end
			else if (char_pixel == 3'b111) begin
				shift_low <= 1'b0;
				end
			end

// serialize the CHARACTER MODE data
always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			char_pix = 1'b0;
			latched_low_char_data = 4'h0;
			latched_char_data  = 8'h00;
		end

	else if (shift_high)
		begin
			char_pix = latched_char_data [7];
			latched_char_data [7] = latched_char_data [6];
			latched_char_data [6] = latched_char_data [5];
			latched_char_data [5] = latched_char_data [4];
			latched_char_data [4] = latched_char_data [7];
				if(latch_low_data) begin
					latched_low_char_data [3:0] = latched_char_data [3:0];
					end
				else begin
					latched_low_char_data [3:0] = latched_low_char_data [3:0];
					end
			end

	else if (shift_low)
		begin
			char_pix = latched_low_char_data [3];
			latched_low_char_data [3] = latched_low_char_data [2];
			latched_low_char_data [2] = latched_low_char_data [1];
			latched_low_char_data [1] = latched_low_char_data [0];
			latched_low_char_data [0] = latched_low_char_data [3];
				if (latch_data) begin
					latched_char_data [7:0] = char_gen_rom_data[7:0];
					end
				else begin
					latched_char_data [7:0] = latched_char_data [7:0];
					end
				end
	 else 
	 	begin
		latched_low_char_data [3:0] = latched_low_char_data [3:0];
		latched_char_data [7:0] = latched_char_data [7:0];
		char_pix = char_pix;
		end
	end


// replicate the data to every bit in the output byte
always @ (char_pix)begin
	char_mode_data = {8{char_pix}};
	end

endmodule //CHARACTER_MODE