coregen.prj

Viertex 2 开发板的接口程序

#COREGen Project File
#Wed Aug 18 14:16:54 CDT 2004
overwritefiles=Default
blkmemsp_v5_0|Xilinx,\ Inc.|5.0=true
sid_v3_1|Xilinx,\ Inc.|3.1=true
decode_8b10b_v5_0|Xilinx,\ Inc.|5.0=true
C_REG_FD_V6_0|Xilinx,\ Inc.|6.0=true
C_REG_FD_V3_0|Xilinx,\ Inc.|3.0=false
C_MUX_BIT_V5_0|Xilinx,\ Inc.|5.0=false
convolution_v2_0|Xilinx,\ Inc.|2.0=false
pci32_v3_0|Xilinx,\ Inc.|3.0=true
C_TWOS_COMP_V4_0|Xilinx,\ Inc.|4.0=false
C_SHIFT_FD_V6_0|Xilinx,\ Inc.|6.0=true
C_DDS_V4_2|Xilinx,\ Inc.|4.2=true
gig_eth_pcs_pma_v4_0|Xilinx,\ Inc.|4.0=true
xlnx_PCI32sII|Xilinx,\ Inc.|3.0=false
C_ACCUM_V5_0|Xilinx,\ Inc.|5.0=false
ten_gig_eth_mac_v4_0|Xilinx,\ Inc.|4.0=true
C_GATE_BIT_BUS_V6_0|Xilinx,\ Inc.|6.0=true
xlnx_pci_express_x1|Xilinx,\ Inc.|1.0=true
C_GATE_BIT_BUS_V3_0|Xilinx,\ Inc.|3.0=false
xilinxfamily=Virtex2
C_DIST_MEM_V4_1|Xilinx,\ Inc.|4.1=false
C_COUNTER_BINARY_V5_0|Xilinx,\ Inc.|5.0=false
C_COUNTER_BINARY_V2_0|Xilinx,\ Inc.|2.0=false
C_ADDSUB_V4_0|Xilinx,\ Inc.|4.0=false
outputoption=DesignFlow
C_MUX_SLICE_BUFE_V2_0|Xilinx,\ Inc.|2.0=false
dividervht|Xilinx,\ Inc.|2.0=true
C_GATE_BIT_V4_0|Xilinx,\ Inc.|4.0=false
simvendor=ModelSim
mult_gen_v6_0|Xilinx,\ Inc.|6.0=true
C_MUX_BUS_V2_0|Xilinx,\ Inc.|2.0=false
vfft64v2|Xilinx,\ Inc.|2.0=true
C_DA_FIR_V7_0|Xilinx,\ Inc.|7.0=false
mac_v2_0|Xilinx,\ Inc.|2.0=true
C_REG_LD_V6_0|Xilinx,\ Inc.|6.0=true
C_REG_LD_V3_0|Xilinx,\ Inc.|3.0=false
sid_v2_0|Xilinx,\ Inc.|2.0=false
C_MUX_SLICE_BUFT_V2_0|Xilinx,\ Inc.|2.0=false
C_SHIFT_RAM_V6_0|Xilinx,\ Inc.|6.0=true
C_MUX_SLICE_BUFE_V5_0|Xilinx,\ Inc.|5.0=false
C_SHIFT_RAM_V3_0|Xilinx,\ Inc.|3.0=false
ADPCM32_catalog|Xilinx,\ Inc.|1.0=true
C_MUX_BUS_V5_0|Xilinx,\ Inc.|5.0=false
outputproducts=ImpNetlist;ASYSymbol;VHDLSim
cam_v4_0|Xilinx,\ Inc.|4.0=true
C_MAC_FIR_V2_0|Xilinx,\ Inc.|2.0=false
C_COMPARE_V4_0|Xilinx,\ Inc.|4.0=false
C_DA_2D_DCT_V2_0|Xilinx,\ Inc.|2.0=true
C_BIT_CORRELATOR_V3_0|Xilinx,\ Inc.|3.0=true
cordic_v2_0|Xilinx,\ Inc.|2.0=true
xlnx_PCI64v|Xilinx,\ Inc.|3.0=false
fileversion=4
viterbi_v3_0|Xilinx,\ Inc.|3.0=true
decode_8b10b_v4_0|Xilinx,\ Inc.|4.0=false
C_DIST_MEM_V3_0|Xilinx,\ Inc.|3.0=false
C_MUX_SLICE_BUFT_V5_0|Xilinx,\ Inc.|5.0=false
C_REG_FD_V2_0|Xilinx,\ Inc.|2.0=false
encode_8b10b_v4_0|Xilinx,\ Inc.|4.0=true
xapp265|Xilinx,\ Inc.|1.1=true
C_DECODE_BINARY_V5_0|Xilinx,\ Inc.|5.0=false
rs_decoder_v4_0|Xilinx,\ Inc.|4.0=false
C_SHIFT_FD_V2_0|Xilinx,\ Inc.|2.0=false
C_DECODE_BINARY_V2_0|Xilinx,\ Inc.|2.0=false
C_GATE_BUS_V4_0|Xilinx,\ Inc.|4.0=false
blkmemdp_v3_0|Xilinx,\ Inc.|3.0=false
posphyl3_link_v1_0|Xilinx,\ Inc.|3.2=true
C_MAC_V3_0|Xilinx,\ Inc.|3.0=true
sync_fifo_v2_0|Xilinx,\ Inc.|2.0=false
blkmemsp_v4_0|Xilinx,\ Inc.|4.0=false
C_DIST_MEM_V6_0|Xilinx,\ Inc.|6.0=true
C_REG_FD_V5_0|Xilinx,\ Inc.|5.0=false
C_MUX_BIT_V4_0|Xilinx,\ Inc.|4.0=false
C_TWOS_COMP_V3_0|Xilinx,\ Inc.|3.0=false
posphyl4_v6_0_1|Xilinx,\ Inc.|6.0.1=true
C_SHIFT_FD_V5_0|Xilinx,\ Inc.|5.0=false
formalverification=None
C_ACCUM_V4_0|Xilinx,\ Inc.|4.0=false
C_GATE_BIT_BUS_V5_0|Xilinx,\ Inc.|5.0=false
C_GATE_BIT_BUS_V2_0|Xilinx,\ Inc.|2.0=false
vfft1024|Xilinx,\ Inc.|1.0=true
C_COUNTER_BINARY_V4_0|Xilinx,\ Inc.|4.0=false
C_ADDSUB_V3_0|Xilinx,\ Inc.|3.0=false
vfft1024v2|Xilinx,\ Inc.|2.0=true
C_MUX_SLICE_BUFE_V4_0|Xilinx,\ Inc.|4.0=false
C_SHIFT_RAM_V2_0|Xilinx,\ Inc.|2.0=false
xfft_v2_0|Xilinx,\ Inc.|2.0=false
designflow=VHDL
C_GATE_BIT_V3_0|Xilinx,\ Inc.|3.0=false
rs_decoder_v4_1|Xilinx,\ Inc.|4.1=true
mult_gen_v5_0|Xilinx,\ Inc.|5.0=false
C_TWOS_COMP_V6_0|Xilinx,\ Inc.|6.0=true
xlnx_pci64_dk|Xilinx,\ Inc.|1.0=true
vfft64|Xilinx,\ Inc.|1.0=true
C_DDC_V1_0|Xilinx,\ Inc.|1.0=true
C_DA_FIR_V6_0|Xilinx,\ Inc.|6.0=false
C_REG_LD_V5_0|Xilinx,\ Inc.|5.0=false
C_REG_LD_V2_0|Xilinx,\ Inc.|2.0=false
lfsr_v3_0|Xilinx,\ Inc.|3.0=true
lockedprops=
C_ADDSUB_V6_0|Xilinx,\ Inc.|6.0=true
C_CIC_V3_0|Xilinx,\ Inc.|3.0=true
xfft_v2_1|Xilinx,\ Inc.|2.1=true
C_SHIFT_RAM_V5_0|Xilinx,\ Inc.|5.0=false
blkmemdp_v3_2|Xilinx,\ Inc.|3.2=false
async_fifo_v5_0|Xilinx,\ Inc.|5.0=false
C_GATE_BIT_V6_0|Xilinx,\ Inc.|6.0=true
simulationoutputproducts=VHDL
C_MUX_BUS_V4_0|Xilinx,\ Inc.|4.0=false
C_SIN_COS_V4_0|Xilinx,\ Inc.|4.0=false
HDLC32_catalog|Xilinx,\ Inc.|1.0=true
busformat=BusFormatAngleBracketNotRipped
cam_v3_0|Xilinx,\ Inc.|3.0=false
vfft256v2|Xilinx,\ Inc.|2.0=true
C_MAC_FIR_V1_0|Xilinx,\ Inc.|1.0=false
C_COMPARE_V3_0|Xilinx,\ Inc.|3.0=false
vfft16|Xilinx,\ Inc.|1.0=true
xlnx_PCI64s2|Xilinx,\ Inc.|3.0=false
cordic_v1_0|Xilinx,\ Inc.|1.0=false
flowvendor=Foundation_iSE
magicnumber=-1172307782
C_DIST_MEM_V2_0|Xilinx,\ Inc.|2.0=false
viterbi_v2_0|Xilinx,\ Inc.|2.0=false
C_MUX_SLICE_BUFT_V4_0|Xilinx,\ Inc.|4.0=false
encode_8b10b_v3_0|Xilinx,\ Inc.|3.0=false
fifo_generator_v1_0|Xilinx,\ Inc.|1.0=true
C_SIN_COS_V4_1|Xilinx,\ Inc.|4.1=false
HDLC1_catalog|Xilinx,\ Inc.|1.0=true
C_DECODE_BINARY_V4_0|Xilinx,\ Inc.|4.0=false
rs_encoder_v4_0|Xilinx,\ Inc.|4.0=false
rs_decoder_v3_0|Xilinx,\ Inc.|3.0=false
blkmemdp_v5_0|Xilinx,\ Inc.|5.0=true
C_GATE_BUS_V3_0|Xilinx,\ Inc.|3.0=false
sync_fifo_v4_0|Xilinx,\ Inc.|4.0=true
C_MAC_FIR_V4_0|Xilinx,\ Inc.|4.0=false
C_ACCUM_V3_0|Xilinx,\ Inc.|3.0=false
tcc_decoder_v1_0|Xilinx,\ Inc.|1.0=true
sync_fifo_v1_0|Xilinx,\ Inc.|1.0=false
C_COMPARE_V6_0|Xilinx,\ Inc.|6.0=true
cordic_v1_1|Xilinx,\ Inc.|1.1=false
blkmemsp_v3_0|Xilinx,\ Inc.|3.0=false
async_fifo_v5_1|Xilinx,\ Inc.|5.1=true
C_DIST_MEM_V5_0|Xilinx,\ Inc.|5.0=false
C_REG_FD_V4_0|Xilinx,\ Inc.|4.0=false
C_MUX_BIT_V6_0|Xilinx,\ Inc.|6.0=true
C_MUX_BIT_V3_0|Xilinx,\ Inc.|3.0=false
convolution_v3_0|Xilinx,\ Inc.|3.0=true
rs_encoder_v4_1|Xilinx,\ Inc.|4.1=true
mult_gen_v4_0|Xilinx,\ Inc.|4.0=false
xfft1024_v1_1|Xilinx,\ Inc.|1.1=true
C_TWOS_COMP_V2_0|Xilinx,\ Inc.|2.0=false
C_SHIFT_FD_V4_0|Xilinx,\ Inc.|4.0=false
flexbus4_v1_0|Xilinx,\ Inc.|1.0=false
C_GATE_BUS_V6_0|Xilinx,\ Inc.|6.0=true
C_ACCUM_V6_0|Xilinx,\ Inc.|6.0=true
C_GATE_BIT_BUS_V4_0|Xilinx,\ Inc.|4.0=false
C_DIST_MEM_V5_1|Xilinx,\ Inc.|5.1=false
C_COUNTER_BINARY_V3_0|Xilinx,\ Inc.|3.0=false
lfsr_v2_0|Xilinx,\ Inc.|2.0=false
C_ADDSUB_V5_0|Xilinx,\ Inc.|5.0=false
C_ADDSUB_V2_0|Xilinx,\ Inc.|2.0=false
C_SIN_COS_V4_2|Xilinx,\ Inc.|4.2=true
C_MUX_SLICE_BUFE_V3_0|Xilinx,\ Inc.|3.0=false
xaui_v4_0|Xilinx,\ Inc.|4.0=true
vfft16v2|Xilinx,\ Inc.|2.0=true
C_GATE_BIT_V5_0|Xilinx,\ Inc.|5.0=false
xlnx_PCIX64_virtex_e_ii|Xilinx,\ Inc.|5.0=true
C_GATE_BIT_V2_0|Xilinx,\ Inc.|2.0=false
C_MUX_BUS_V3_0|Xilinx,\ Inc.|3.0=false
C_TWOS_COMP_V5_0|Xilinx,\ Inc.|5.0=false
posphyl4_lite_v2_0|Xilinx,\ Inc.|2.0=true
C_DA_FIR_V8_0|Xilinx,\ Inc.|8.0=true
C_DA_FIR_V5_0|Xilinx,\ Inc.|5.0=false
xlnx_PCI64|Xilinx,\ Inc.|3.0=true
C_DDS_V4_0|Xilinx,\ Inc.|4.0=false
C_REG_LD_V4_0|Xilinx,\ Inc.|4.0=false
C_COUNTER_BINARY_V6_0|Xilinx,\ Inc.|6.0=true
C_DA_1D_DCT_V2_1|Xilinx,\ Inc.|2.1=true
C_MUX_SLICE_BUFE_V6_0|Xilinx,\ Inc.|6.0=true
C_SHIFT_RAM_V4_0|Xilinx,\ Inc.|4.0=false
async_fifo_v4_0|Xilinx,\ Inc.|4.0=false
xlnx_PCI32v|Xilinx,\ Inc.|3.0=false
vfft32_v3_0|Xilinx,\ Inc.|3.0=true
C_MUX_BUS_V6_0|Xilinx,\ Inc.|6.0=true
blkmemsp_v3_2|Xilinx,\ Inc.|3.2=false
C_COMPARE_V2_0|Xilinx,\ Inc.|2.0=false
C_DDS_V4_1|Xilinx,\ Inc.|4.1=false
vfft256|Xilinx,\ Inc.|1.0=true
simelaboptions=
C_DIST_MEM_V4_0|Xilinx,\ Inc.|4.0=false
sid_v3_0|Xilinx,\ Inc.|3.0=false
C_MUX_SLICE_BUFT_V6_0|Xilinx,\ Inc.|6.0=true
xilinxsubfamily=Virtex2
C_MUX_SLICE_BUFT_V3_0|Xilinx,\ Inc.|3.0=false
C_MUX_BIT_V2_0|Xilinx,\ Inc.|2.0=false
gig_eth_mac_v4_0|Xilinx,\ Inc.|4.0=true
C_DECODE_BINARY_V6_0|Xilinx,\ Inc.|6.0=true
C_SHIFT_FD_V3_0|Xilinx,\ Inc.|3.0=false
corelibraryid=0
C_DECODE_BINARY_V3_0|Xilinx,\ Inc.|3.0=false
rs_encoder_v3_0|Xilinx,\ Inc.|3.0=false
C_GATE_BUS_V5_0|Xilinx,\ Inc.|5.0=false
C_GATE_BUS_V2_0|Xilinx,\ Inc.|2.0=false
blkmemdp_v4_0|Xilinx,\ Inc.|4.0=false
sync_fifo_v3_0|Xilinx,\ Inc.|3.0=false
C_ACCUM_V2_0|Xilinx,\ Inc.|2.0=false
C_MAC_FIR_V3_0|Xilinx,\ Inc.|3.0=true
tcc_encoder_v1_0|Xilinx,\ Inc.|1.0=true
C_COMPARE_V5_0|Xilinx,\ Inc.|5.0=false