ramp_bkup.v

Viertex 2 开发板的接口程序

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//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : White to Black Ramp Video Test Pattern
   Project    : XUP Virtex-II Pro Development System 
-------------------------------------------------------------------------------
   File       : RAMP.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/12
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       : VIDEO_RAM.v
-------------------------------------------------------------------------------
   Used by    : HW_BIST.v
-------------------------------------------------------------------------------
   Description: This module creates a white to black ramp video test pattern.
   				The number of ramps will depend on the video mode but a 
				640 x 480 display will result in 2.5 ramps. Each ramp is 256 pixels
			 	long. The ramp data is created from the pixel count output
				of the video timing generator.
	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.


-------------------------------------------------------------------------------
*/

module RAMP
(
pixel_clock,
pixel_count,
vga_ramp_data
);
input pixel_clock;
input [10:0] pixel_count;
output [7:0] vga_ramp_data;

// create the white to black ramp data in memory
wire [12:0]	write_ramp_addr;
wire [12:0]	read_ramp_addr; 
wire read_enable = 1'b1;
wire write_enable = 1'b1;
wire [7:0] write_ramp_data;

assign 	write_ramp_addr[12:0] 	= {5'b00000, pixel_count[7:0]};
assign 	write_ramp_data[7:0] 	= ~pixel_count[7:0];
assign 	read_ramp_addr[12:0] 	= {5'b00000, pixel_count[7:0]};

VIDEO_RAM RAMP_RAM(
pixel_clock,		// read clock
vga_ramp_data,		// read data
read_ramp_addr,		// read address
read_enable,
write_ramp_data,	// write data
write_ramp_addr,	// write address
pixel_clock,		// write clock
write_enable
);
endmodule // RAMP