hw_bist.v

Viertex 2 开发板的接口程序

//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : Built In Self Test
   Project    : XUP Virtex-II Pro Development System 
-------------------------------------------------------------------------------
   File       : HW_BIST.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/13
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       : CLOCK_GEN.v CLOCK_AUDIO_PB_SWITCH_TEST.v EXPANSION_PORT_TEST.v
				PS2.v SILICON_SERIAL_NUMBER.v COLOR_BARS.v RAMP.v CHAR_MODE.v
				SVGA_TIMING_GENERATION.v VIDEO_OUT.v
-------------------------------------------------------------------------------
   Used by    : 
-------------------------------------------------------------------------------
 Description: This is the top level module for the non-processor centric portions
 			  of the Built In Self Test (Golden Design) for the XUP Virtex-II Pro 
			  Development System.

			  This test covers the LEDs, pushbuttons, DIP switches, Audio power
			  amplifier, SVGA output and the expansion ports.

			  When the test first runs, the LEDs indicate the presence of the
			  board clocks and DCMs acheiving lock, and after ~5 seconds the
			  LEDs switch to show the status of the DIP switches.

			  When each pushbutton is pressed a different tone will be produced from 
			  the audio amplifier output.

			  The board serial number, keyboard and mouse port data will be displayed
			  on the SVGA output along with a set of color bars and a white to black
			  repeating ramp. The user can augment the character mode area of the display
			  with 12 rows of text, character address 640-1599 using the external character
			  mode control signals on the CHAR_MODE module.

			  The verification of the expansion ports require the use of an oscilloscope.
			  A 20nS pulse with a 1.6uS period should be observed on each signal pin.

			  This design is to be merged with a processor centric design that will
			  test the Ethernet port, the MGTs the SDRAM (if present), the RS232 port
			  and the PCM audio path.
 
	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.

-------------------------------------------------------------------------------
*/
module HW_BIST 
(
MGT_CLK_P,
MGT_CLK_N,
SYSTEM_CLOCK,
FPGA_SYSTEMACE_CLOCK,
ck_100MHz,
ck_100MHz_90,
ck_100MHz_180,
ck_100MHz_270,
ck_75MHz,
ck_32MHz,
AUDIO_RESET_OUT_Z,
USER_LED0,
USER_LED1,
USER_LED2,
USER_LED3,
BEEP_TONE_IN,
PB_UP,
PB_DOWN,
PB_LEFT,
PB_RIGHT,
PB_ENTER,
DIP_SW0,
DIP_SW1,
DIP_SW2,
DIP_SW3,
CPU_RESET,
SSN_DATA,
EXPANSION_PORT,
HIGH_SPEED_PORT,
PS2_KBD_CLK,
PS2_KBD_DATA,
PS2_MOUSE_CLK,
PS2_MOUSE_DATA,
VGA_OUT_PIXEL_CLOCK,
VGA_COMP_SYNCH,
VGA_OUT_BLANK_Z,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE,
// signals for PPC  & peripherals
DIP_SW_PS2_BUS_IN,
dcms_locked,
CPU_RESET_OUT,
hi_dword_sn_data,
lo_dword_sn_data,
expan_port_rd_data_lo,
expan_port_rd_data_hi,
ac97_rst_sft_ps2_out
);


input	MGT_CLK_P;				// 75MHz LVDS DIFFERENTIAL CLOCK FOR SATA
input	MGT_CLK_N;
input	SYSTEM_CLOCK;			// 100MHz LVTTL SYSTEM CLOCK
input	FPGA_SYSTEMACE_CLOCK;	// 32MHz SYSTEMACE CLOCK


output 	ck_100MHz;
output	ck_100MHz_90;
output	ck_100MHz_180;
output	ck_100MHz_270;
output 	ck_75MHz;
output 	ck_32MHz;
output  dcms_locked;

output 	AUDIO_RESET_OUT_Z;			// RESET FOR THE AC97 AUDIO CODEC
output 	BEEP_TONE_IN;
output	USER_LED0;				// DCM LOCKED 				/ DIP_SW0 STATUS
output	USER_LED1;				// SYSTEMACE CLOCK ACTIVE 	/ DIP_SW1 STATUS
output	USER_LED2;				// MGT CLOCK ACTIVE 		/ DIP_SW2 STATUS
output	USER_LED3;				// SYSTEM CLOCK ACTIVE 		/ DIP_SW3 STATUS

input 	PB_UP;					// PUSH BUTTON INPUTS
input 	PB_DOWN;
input 	PB_LEFT;
input 	PB_RIGHT;
input 	PB_ENTER;
input 	DIP_SW0;				// DIP SWITCH INPUTS
input 	DIP_SW1;
input 	DIP_SW2;
input 	DIP_SW3;
input 	CPU_RESET;				// CPU RESET PUSH BUTTON INPUT
input [0:12]  ac97_rst_sft_ps2_out; // PPC control of audio reset & PS2 software test control/data and shift dat to expandsion port

inout			SSN_DATA;		// one wire interface

output [79:0] EXPANSION_PORT;	// low-speed Digilent port and header pins
output [42:0] HIGH_SPEED_PORT;	// high-speed Digilent port


output [0:12] DIP_SW_PS2_BUS_IN;   // PPC access of dip switches & ps2 inputs back to PPC for software testing

inout	PS2_KBD_CLK;			// PS/2 keyboard clock
inout	PS2_KBD_DATA;			// PS/2 keyboard data
inout	PS2_MOUSE_CLK;			// PS/2 mouse clock
inout	PS2_MOUSE_DATA;			// PS/2 mouse data

output 			VGA_OUT_PIXEL_CLOCK;// pixel clock for the video DAC
output			VGA_COMP_SYNCH;		// composite sync for the video DAC
output 			VGA_OUT_BLANK_Z;	// composite blanking for the video DAC
output 			VGA_HSYNCH;			// horizontal sync for the VGA output connector
output			VGA_VSYNCH;			// vertical sync for the VGA output connector
output [7:0] 	VGA_OUT_RED;		// RED DAC data
output [7:0] 	VGA_OUT_GREEN;		// GREEN DAC data
output [7:0] 	VGA_OUT_BLUE;		// BLUE DAC data
output          CPU_RESET_OUT;      // cpu reset to PPC logic

output [0:31] hi_dword_sn_data;    // serial number read data
output [0:31] lo_dword_sn_data;    // serial number read data

output [0:31] expan_port_rd_data_lo;  // expansion ports read back test data
output [0:31] expan_port_rd_data_hi;   // high speed ports read back test data


wire 	_100MHz_clock;			// buffered SYSTEM CLOCK
wire 	_75MHz_clock;			// buffered MGT rate CLOCK
wire	_33MHz_clock;			// 1/3 * SYSTEM_CLOCK
wire	_32MHz_clock;			// buffered FPGA_SYSTEMACE_CLOCK
wire	_100_90_clock;
wire	_100_180_clock;
wire	_100_270_clock;
wire	reset;					// reset asserted when DCMs are NOT LOCKED

wire 	[7:0] vga_red_bar_data;	// color bar video data
wire 	[7:0] vga_green_bar_data;
wire 	[7:0] vga_blue_bar_data;

wire	[7:0] vga_ramp_data;	// white to black video data

wire	[7:0] char_mode_data;	// character mode video data

// internal video timing signals
wire 				h_synch_delay;
wire 				v_synch_delay;
wire 				comp_synch;
wire 				blank;
wire 	[2:0]		char_line_count;	// the line number within a character block 0-8
wire 	[12:0]		char_mode_address;	// the block address of the character in character mode
wire 	[13:0]		char_address;		// the block address of the character in character mode
assign char_mode_address[12:0] = char_address[12:0];
wire 	[2:0]		char_pixel;			// the pixel number within a character block 0-8
wire 	[10:0]		pixel_count;		// bit mapped pixel position within the line
wire 	[9:0]		line_count;			// bit mapped line number in a frame lines within the frame

wire 	[11:0]	ext_char_addr;			// character address for character data
wire	[7:0]  	ext_char_data;			// external character data
wire			ext_write_enable;		// write enable for external character data
wire			ext_request;			// request for external access to the character mode RAM
wire            AUDIO_RESET_Z;


// external character mode is not used
assign ext_char_addr =0;
assign ext_char_data = 0;
assign ext_write_enable = 0;
assign ext_request =0;
assign 	ck_100MHz = _100MHz_clock;
assign 	ck_75MHz  = _75MHz_clock;
assign 	ck_32MHz  = _32MHz_clock;
assign	ck_100MHz_90 = _100_90_clock;
assign	ck_100MHz_180 =_100_180_clock;
assign	ck_100MHz_270 =_100_270_clock;
assign PBUTTON_BUS ={PB_UP, PB_DOWN, PB_LEFT, PB_RIGHT}  ;  // pass through to orinially  by Aurora deisgn as bus now unused
assign CPU_RESET_OUT = CPU_RESET;                           // pass through to PPC


// silicon serial number signals
wire	[7:0]	sn_12;
wire	[7:0]	sn_11;
wire	[7:0]	sn_10;
wire	[7:0]	sn_9;
wire	[7:0]	sn_8;
wire	[7:0]	sn_7;
wire	[7:0]	sn_6;
wire	[7:0]	sn_5;
wire	[7:0]	sn_4;
wire	[7:0]	sn_3;
wire	[7:0]	sn_2;
wire	[7:0]	sn_1;
wire    [47:0]  sn_data;

assign hi_dword_sn_data= {16'h0000, sn_data[47:32]}; // software access to serial number data
assign lo_dword_sn_data = sn_data[31:0];             // software access to serial number data

// PS/2 port signals
wire	[7:0]	ps2_mouse_ascii;
wire	[7:0]	ps2_kbd_ascii;
// software testing signals
wire	PS2_M_CLK_IN;
wire	PS2_K_CLK_IN;
wire	PS2_M_DATA_IN; 
wire	PS2_K_DATA_IN;
wire	TST_PS2;
wire	PS2_M_CLK_OUT; 
wire	PS2_K_CLK_OUT;
wire	PS2_M_DATA_OUT; 
wire	PS2_K_DATA_OUT;
wire	hw_test_enable;
wire	sft_test_enable;
wire	sft_test_data;
wire	sft_test_clk;

assign	TST_PS2 = ac97_rst_sft_ps2_out[3]; // software overide output for testing of ps 2 ports
assign	PS2_M_CLK_OUT = ac97_rst_sft_ps2_out[4]; // software overide output for testing of ps 2 ports
assign	PS2_K_CLK_OUT = ac97_rst_sft_ps2_out[5];// software overide output for testing of ps 2 ports
assign	PS2_M_DATA_OUT = ac97_rst_sft_ps2_out[6]; // software overide output for testing of ps 2 ports
assign	PS2_K_DATA_OUT = ac97_rst_sft_ps2_out[7];// software overide output for testing of ps 2 ports
assign	hw_test_enable = ac97_rst_sft_ps2_out[8]; //  software enables hardware driven expansion & high speed port walking ones test 
assign	sft_test_enable = ac97_rst_sft_ps2_out[9]; // software controlled not used yet
assign	sft_test_data = ac97_rst_sft_ps2_out[10]; // software driven data to shift register for softeware diven expansion & high speed posrt loop back test
assign	sft_test_clk = ac97_rst_sft_ps2_out[11]; // software driven clock to shift register for softeware diven expansion & high speed posrt loop back test
assign  AUDIO_RESET_OUT_Z =  AUDIO_RESET_Z |  ac97_rst_sft_ps2_out[12]; // comb logic for sftwre control of AC97 reset
assign DIP_SW_PS2_BUS_IN = {PS2_M_CLK_IN, PS2_K_CLK_IN, PS2_M_DATA_IN, PS2_K_DATA_IN, PB_UP, PB_DOWN, PB_LEFT, PB_RIGHT, PB_ENTER, DIP_SW0, DIP_SW1, DIP_SW2, DIP_SW3};

// instantiate the clock generation module
CLOCK_GEN CLOCK_GEN 
(
MGT_CLK_P,
MGT_CLK_N,
SYSTEM_CLOCK,
FPGA_SYSTEMACE_CLOCK,


_100MHz_clock,
_100_90_clock,
_100_180_clock,
_100_270_clock,
_75MHz_clock,
_32MHz_clock,
_25MHz_clock,
reset,
dcms_locked
);

// instantiate the test module for the clock presence, 
// LEDs, pushbuttons, switches and audio amp

CLOCK_AUDIO_PB_SWITCH_TEST CLOCK_AUDIO_PB_SWITCH_TEST
(
AUDIO_RESET_Z,
USER_LED0,
USER_LED1,
USER_LED2,
USER_LED3,
BEEP_TONE_IN,
PB_UP,
PB_DOWN,
PB_LEFT,
PB_RIGHT,
PB_ENTER,
DIP_SW0,
DIP_SW1,
DIP_SW2,
DIP_SW3,
CPU_RESET,
_100MHz_clock,
_75MHz_clock,
_32MHz_clock,
reset
);

// instantiate the test module for the expansion ports
EXPANSION_PORT_TEST EXPANSION_PORT_TEST
(
_100MHz_clock,
reset,
hw_test_enable,
sft_test_enable,
sft_test_data,
sft_test_clk,
expan_port_rd_data_lo,
expan_port_rd_data_hi,
EXPANSION_PORT,
HIGH_SPEED_PORT
);

// instantiate the PS/2 port interfaces
PS2 PS2 
(
_25MHz_clock,
reset,
PS2_KBD_CLK,
PS2_KBD_DATA,
ps2_kbd_ascii,
PS2_MOUSE_CLK,
PS2_MOUSE_DATA,
ps2_mouse_ascii,
PS2_M_CLK_IN, 
PS2_K_CLK_IN,
PS2_M_DATA_IN, 
PS2_K_DATA_IN,
TST_PS2,
PS2_M_CLK_OUT, 
PS2_K_CLK_OUT,
PS2_M_DATA_OUT, 
PS2_K_DATA_OUT
);

// instantiate the Silicon Serial Number test interface
SILICON_SERIAL_NUMBER SILICON_SERIAL_NUMBER(
_25MHz_clock,
reset,
SSN_DATA,
sn_1,
sn_2,
sn_3,
sn_4,
sn_5,
sn_6,
sn_7,
sn_8,
sn_9,
sn_10,
sn_11,
sn_12,
sn_data
);

// instantiate the bit mapped mode video color bar generator
COLOR_BARS COLOR_BARS
(
pixel_count,
_25MHz_clock,
vga_red_bar_data,
vga_green_bar_data,
vga_blue_bar_data
);

// instantiate the bit mapped mode white to black video ramp generator
RAMP RAMP
(
_25MHz_clock,
pixel_count,
vga_ramp_data
);

// instantiate the character mode video data generator
CHAR_MODE CHAR_MODE
(
char_mode_address,
char_line_count,
char_pixel,
_25MHz_clock,
//_100MHz_clock,
_75MHz_clock,
reset,
sn_1,
sn_2,
sn_3,
sn_4,
sn_5,
sn_6,
sn_7,
sn_8,
sn_9,
sn_10,
sn_11,
sn_12,
ps2_mouse_ascii,
ps2_kbd_ascii,
char_mode_data,
ext_char_addr,
ext_char_data,
ext_write_enable,
ext_request
);

// instantiate the video output mux
VIDEO_OUT VIDEO_OUT
(
_25MHz_clock,
reset,
VGA_OUT_PIXEL_CLOCK,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_COMP_SYNCH,
VGA_OUT_BLANK_Z,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE,
char_mode_data,
vga_red_bar_data,
vga_green_bar_data,
vga_blue_bar_data,
vga_ramp_data,
h_synch_delay,
v_synch_delay,
comp_synch,
blank,
line_count
);

// instantiate the video timing generator
SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION
(
_25MHz_clock,
reset,
h_synch_delay,
v_synch_delay,
comp_synch,
blank,
char_line_count,
char_address,
char_pixel,
pixel_count,
line_count
);
endmodule //HW_BIST