bitreg.v

Viertex 2 开发板的接口程序

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//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
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/*
------------------------------------------------------------------------------
-- Title      : Addressable Bit Register
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : bitreg.v
-- Company    : Xilinx Inc
-- Created    : 2001/03/15
-- Last update: 2001/03/15
-- Copyright  : (c) Xilinx Inc 2001
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_master.v
-------------------------------------------------------------------------------
-- Description:  A eight bit addressable register
-------------------------------------------------------------------------------
*/


module BITREG (clk, reset, din, en, dout);

input clk;
input reset;
input din;
input [7:0] en;
output [7:0] dout;

reg [7:0] dout;

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[0] <= 1'b0;
		end
	else if (en[0]) begin
		dout[0] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[1] <= 1'b0;
		end
	else if (en[1]) begin
		dout[1] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[2] <= 1'b0;
		end
	else if (en[2]) begin
		dout[2] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[3] <= 1'b0;
		end
	else if (en[3]) begin
		dout[3] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[4] <= 1'b0;
		end
	else if (en[4]) begin
		dout[4] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[5] <= 1'b0;
		end
	else if (en[5]) begin
		dout[5] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[6] <= 1'b0;
		end
	else if (en[6]) begin
		dout[6] <= din;
		end
	end

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		dout[7] <= 1'b0;
		end
	else if (en[7]) begin
		dout[7] <= din;
		end
	end
endmodule