black_boxes.v

来自「Viertex 2 开发板的接口程序」· Verilog 代码 · 共 67 行

module SRL16(Q, A0, A1, A2, A3, CLK, D); // synthesis syn_black_box
output Q;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule

module IBUFGDS(O, I, IB); // synthesis syn_black_box
output O;
input I;
input IB;
endmodule


module IBUFG(O, I); // synthesis syn_black_box
output O;
input I;
endmodule

module BUFG(O, I); // synthesis syn_black_box
output O;
input I;
endmodule

module DCM(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST,
  CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS); // synthesis syn_black_box
input CLKFB, CLKIN, DSSEN;
input PSCLK, PSEN, PSINCDEC, RST;
output CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180;
output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
output [7:0] STATUS;
endmodule


module RAMB16_S2_S2(DOA, DOB, ADDRA, CLKA, DIA, ENA, SSRA, WEA, ADDRB, CLKB, DIB, ENB, SSRB, WEB); // synthesis syn_black_box
output [1:0] DOA;
output [1:0] DOB;
input [12:0] ADDRA;
input CLKA;
input [1:0] DIA;
input ENA;
input SSRA;
input WEA;
input [12:0] ADDRB;
input CLKB;
input [1:0] DIB;
input ENB;
input SSRB;
input WEB;
endmodule


module RAMB16_S9(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR); // synthesis syn_black_box
output [7:0] DO;
output [0:0] DOP;
input [10:0] ADDR;
input [7:0] DI;
input [0:0] DIP;
input EN;
input CLK;
input WE;
input SSR;
endmodule