color_bars.v

Viertex 2 开发板的接口程序

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//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
   Title      : Color Bar Video Test Pattern
   Project    : XUP Virtex-II Pro Development System 
-------------------------------------------------------------------------------
   File       : COLOR_BARS.v
   Company    : Xilinx, Inc.
   Created    : 2004/08/12
   Last Update: 2004/08/12
   Copyright  : (c) Xilinx Inc, 2004
-------------------------------------------------------------------------------
   Uses       : VIDEO_RAM.v
-------------------------------------------------------------------------------
   Used by    : HW_BIST.v
-------------------------------------------------------------------------------
   Description: This module creates a color bar video test pattern on a 640 x 480
   				display. The color bars are created from the pixel count output
				of the video timing generator.
	Conventions:
		All external port signals are UPPER CASE.
		All internal signals are LOWER CASE and are active HIGH.


-------------------------------------------------------------------------------

*/

module COLOR_BARS
(
pixel_count,
pixel_clock,
vga_red_bar_data,
vga_green_bar_data,
vga_blue_bar_data
);

input [10:0] 	pixel_count;
input 			pixel_clock;
output [7:0]	vga_red_bar_data;
output [7:0]	vga_green_bar_data;
output [7:0]	vga_blue_bar_data;	

reg [7:0]		red_bar_data;
reg [7:0]		green_bar_data;
reg [7:0]		blue_bar_data;

// create the color bars in memory
wire [12:0] write_bar_addr  = {3'b000, pixel_count[9:0]};
wire [12:0] read_bar_addr   = {3'b000, pixel_count[9:0]};
wire		read_enable		= 1'b1;
wire		write_enable		= 1'b1;

always @ (pixel_count) begin
	if (pixel_count < 79) begin			//100% white
			red_bar_data[7:0] 	<= 8'hFF;
			green_bar_data[7:0] <= 8'hFF;
			blue_bar_data[7:0]  <= 8'hFF;
			end
		else if ((pixel_count > 80) & (pixel_count < 159)) begin	//75% yellow
			red_bar_data[7:0] 	<= 8'hBF;
			green_bar_data[7:0] <= 8'hBF;
			blue_bar_data[7:0]  <= 8'h00;
			end
		else if ((pixel_count > 160) & (pixel_count < 239)) begin	//75% cyan
			red_bar_data[7:0] 	<= 8'h00;
			green_bar_data[7:0] <= 8'hBF;
			blue_bar_data[7:0]  <= 8'hBF;
			end
		else if ((pixel_count > 240) & (pixel_count < 319)) begin	//75% green
			red_bar_data[7:0] 	<= 8'h00;
			green_bar_data[7:0] <= 8'hBF;
			blue_bar_data[7:0]  <= 8'h00;
			end
		else if ((pixel_count > 320) & (pixel_count < 399)) begin	//75% magenta
			red_bar_data[7:0] 	<= 8'hBF;
			green_bar_data[7:0] <= 8'h00;
			blue_bar_data[7:0]  <= 8'hBF;
			end
		else if ((pixel_count > 400) & (pixel_count < 479)) begin	//75% red
			red_bar_data[7:0] 	<= 8'hBF;
			green_bar_data[7:0] <= 8'h00;
			blue_bar_data[7:0]  <= 8'h00;
			end
		else if ((pixel_count > 480) * (pixel_count < 559)) begin	//75% blue
			red_bar_data[7:0] 	<= 8'h00;
			green_bar_data[7:0] <= 8'h00;
			blue_bar_data[7:0]  <= 8'hBF;
			end
		else begin													// black
			red_bar_data[7:0] 	<= 8'h00;
			green_bar_data[7:0] <= 8'h00;
			blue_bar_data[7:0]  <= 8'h00;
			end
		end

VIDEO_RAM RED_BAR_RAM(
pixel_clock,		// read clock
vga_red_bar_data,	// read data
read_bar_addr,		// read address
read_enable,
red_bar_data,		// write data
write_bar_addr,		// write address
pixel_clock,		// write clock
write_enable
);

VIDEO_RAM GREEN_BAR_RAM(
pixel_clock,		// read clock
vga_green_bar_data,	// read data
read_bar_addr,		// read address
read_enable,
green_bar_data,		// write data
write_bar_addr,		// write address
pixel_clock,		// write clock
write_enable
);

VIDEO_RAM BLUE_BAR_RAM(
pixel_clock,		// read clock
vga_blue_bar_data,	// read data
read_bar_addr,		// read address
read_enable,
blue_bar_data,		// write data
write_bar_addr,		// write address
pixel_clock,		// write clock		
write_enable
);
endmodule //COLOR_BARS