special_clk_div.v

Viertex 2 开发板的接口程序

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/*
-------------------------------------------------------------------------------
-- Title      : CLOCK DIVIDER
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : special_clk_div.v
-- Company    : Xilinx Inc
-- Created    : 2001/03/15
-- Last update: 2001/03/15
-- Copyright  : (c) Xilinx Inc 2001
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_master.v
-------------------------------------------------------------------------------
-- Description: divide clock input by 32
-------------------------------------------------------------------------------
*/

// use this clock divider until the SRL16 fix works

module SPECIAL_CLK_DIVIDER (reset,clk_in,clk_out);
input reset;
input clk_in;
output clk_out;

reg [15:0] shifter;
reg clk;
wire toggle;
wire clk_out;
wire clock_out;
assign toggle = shifter[15];

always @ (posedge clk_in or posedge reset) begin
	if (reset) begin
		shifter <= 16'h0001;
		end
	else begin
		shifter [15:1] <= shifter [14:0];
		shifter [0] <= shifter[15];
		end
	end

always @ (posedge toggle or posedge reset) begin
	if (reset) begin
		clk <=1'b1;
		end
	else begin
		clk <=!clk_out;
		end
	end


BUFG SPECIAL_CLOCK_BUFFER (
.O  (clk_out),
.I  (clk)
);

endmodule