📄 mystm32_init.c
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// <15=> fSampling=fDTS/32, N=8
// <o12.2..3> TIM1_CCMR2.IC3PSC: Input Capture 3 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o12.0..1> TIM1_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <1=> CC3 configured as input, IC3 mapped on TI3
// <2=> CC3 configured as input, IC3 mapped on TI4
// <3=> CC3 configured as input, IC3 mapped on TRGI
// <o13.9> TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.8> TIM1_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o16> TIM1_CCR3: Capture/compare register 3 <0-65535>
// <i> Set the Compare register value for compare register 3.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 4
// <h> Channel 4 Configuration
// <h> Cannel configured as output
// <o12.15> TIM1_CCMR2.OC4CE: Output Compare 4 Clear enabled
// <o12.12..14> TIM1_CCMR2.OC4M: Output Compare 4 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 4 to active level on match
// <2=> Set channel 4 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o12.11> TIM1_CCMR2.OC4PE: Output Compare 4 Preload enabled
// <o12.10> TIM1_CCMR2.OC4FE: Output Compare 4 Fast enabled
// <o12.8..9> TIM1_CCMR2.CC4S: Capture/compare 4 selection
// <i> Default: CC4 configured as output
// <0=> CC4 configured as output
// <o13.13> TIM1_CCER.CC4P: Capture/compare 4 output Polarity set
// <i> Default: OC4 active high
// <0=> OC4 active high
// <1=> OC4 active low
// <o13.12> TIM1_CCER.CC4E: Capture/compare 4 output enabled
// <i> Default: OC4 not active
// <0=> OC4 not active
// <1=> OC4 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o12.12..15> TIM1_CCMR2.IC4F: Input Capture 4 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o12.10..11> TIM1_CCMR2.IC4PSC: Input Capture 4 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o12.8..9> TIM1_CCMR2.CC4S: Capture/compare 4 selection
// <i> Default: CC4 configured as output
// <0=> CC4 configured as output
// <1=> CC4 configured as input, IC4 mapped on TI4
// <2=> CC4 configured as input, IC4 mapped on TI3
// <3=> CC4 configured as input, IC4 mapped on TRGI
// <o13.13> TIM1_CCER.CC4P: Capture/compare 4 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.12> TIM1_CCER.CC4E: Capture/compare 4 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o17> TIM1_CCR4: Capture/compare register 4 <0-65535>
// <i> Set the Compare register value for compare register 4.
// <i> Default: 0
// </h>
//
// <h> Timer1 Break and dead-time register Configuration (TIM1_BDTR)
// <o18.15> TIM1_BDTR.MOE: Main Output enabled
// <o18.14> TIM1_BDTR.AOE: Automatic Output enabled
// <o18.13> TIM1_BDTR.BKP: Break Polarity active high
// <o18.12> TIM1_BDTR.BKE: Break Inputs enabled
// <o18.11> TIM1_BDTR.OSSR: Off-State Selection for Run mode
// <i> Default: OC/OCN output signal=0
// <0=> OC/OCN output signal=0
// <1=> OC/OCN output signal=1
// <o18.10> TIM1_BDTR.OSSI: Off-State Selection for Idle mode
// <i> Default: OC/OCN output signal=0
// <0=> OC/OCN output signal=0
// <1=> OC/OCN output signal=1
// <o18.8..9> TIM1_BDTR.LOCK: Lock Level <0-3>
// <i> Default: 0 (LOCK OFF)
// <o18.0..7> TIM1_BDTR.DTG: Dead-Time Generator set-up <0x00-0xFF>
// </h>
//
// </e>
// <e3.0> TIM1 interrupts
// <o19.14> TIM1_DIER.TDE: Trigger DMA request enabled
// <o19.12> TIM1_DIER.CC4DE: Capture/Compare 4 DMA request enabled
// <o19.11> TIM1_DIER.CC3DE: Capture/Compare 3 DMA request enabled
// <o19.10> TIM1_DIER.CC2DE: Capture/Compare 2 DMA request enabled
// <o19.9> TIM1_DIER.CC1DE: Capture/Compare 1 DMA request enabled
// <o19.8> TIM1_DIER.UDE: Update DMA request enabled
// <o19.7> TIM1_DIER.BIE: Break interrupt enabled
// <o19.6> TIM1_DIER.TIE: Trigger interrupt enabled
// <o19.5> TIM1_DIER.COMIE: COM interrupt enabled
// <o19.4> TIM1_DIER.CC4IE: Capture/Compare 4 interrupt enabled
// <o19.3> TIM1_DIER.CC3IE: Capture/Compare 3 interrupt enabled
// <o19.2> TIM1_DIER.CC2IE: Capture/Compare 2 interrupt enabled
// <o19.1> TIM1_DIER.CC1IE: Capture/Compare 1 interrupt enabled
// <o19.0> TIM1_DIER.UIE: Update interrupt enabled
// </e>
// </e>
// </e> End of Timer Configuration
#define __TIMER_SETUP 0 // 0
#define __TIMER_USED 0x0001 // 1
#define __TIMER_DETAILS 0x0000 // 2
#define __TIMER_INTERRUPTS 0x0001 // 3
#define __TIM1_PERIOD 0x003E8 // 4
#define __TIM1_PSC 0x0000 // 5
#define __TIM1_ARR 0x0004 // 6
#define __TIM1_RCR 0x0000 // 7
#define __TIM1_CR1 0x0004 // 8
#define __TIM1_CR2 0x0000 // 9
#define __TIM1_SMCR 0x0000 // 10
#define __TIM1_CCMR1 0x0061 // 11
#define __TIM1_CCMR2 0x0068 // 12
#define __TIM1_CCER 0x0000 // 13
#define __TIM1_CCR1 0x0000 // 14
#define __TIM1_CCR2 0x0000 // 15
#define __TIM1_CCR3 0x0000 // 16
#define __TIM1_CCR4 0x0000 // 17
#define __TIM1_BDTR 0x0000 // 18
#define __TIM1_DIER 0x0001 // 19
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#define CFGR_SWS_MASK 0x0000000C // Mask for used SYSCLK
#define CFGR_SW_MASK 0x00000003 // Mask for used SYSCLK
#define CFGR_PLLMULL_MASK 0x003C0000 // Mask for PLL multiplier
#define CFGR_PLLXTPRE_MASK 0x00020000 // Mask for PLL HSE devider
#define CFGR_PLLSRC_MASK 0x00010000 // Mask for PLL clock source
#define CFGR_HPRE_MASK 0x000000F0 // Mask for AHB prescaler
#define CFGR_PRE1_MASK 0x00000700 // Mask for APB1 prescaler
#define CFGR_PRE2_MASK 0x00003800 // Mask for APB2 prescaler
/*----------------------------------------------------------------------------
Define SYSCLK
*----------------------------------------------------------------------------*/
#define __HSI 8000000UL
//#define __HSE 8000000UL
#define __PLLMULL (((__RCC_CFGR_VAL & CFGR_PLLMULL_MASK) >> 18) + 2)
#if ((__RCC_CFGR_VAL & CFGR_SW_MASK) == 0x00)
#define __SYSCLK __HSI // HSI is used as system clock
#elif ((__RCC_CFGR_VAL & CFGR_SW_MASK) == 0x01)
#define __SYSCLK __HSE // HSE is used as system clock
#elif ((__RCC_CFGR_VAL & CFGR_SW_MASK) == 0x02)
#if (__RCC_CFGR_VAL & CFGR_PLLSRC_MASK) // HSE is PLL clock source
#if (__RCC_CFGR_VAL & CFGR_PLLXTPRE_MASK) // HSE/2 is used
#define __SYSCLK ((__HSE >> 1) * __PLLMULL)// SYSCLK = HSE/2 * pllmull
#else // HSE is used
#define __SYSCLK ((__HSE >> 0) * __PLLMULL)// SYSCLK = HSE * pllmul
#endif
#else // HSI/2 is PLL clock source
#define __SYSCLK ((__HSI >> 1) * __PLLMULL) // SYSCLK = HSI/2 * pllmul
#endif
#else
#error "ask for help"
#endif
/*----------------------------------------------------------------------------
Define HCLK
*----------------------------------------------------------------------------*/
#define __HCLKPRESC ((__RCC_CFGR_VAL & CFGR_HPRE_MASK) >> 4)
#if (__HCLKPRESC & 0x08)
#define __HCLK (__SYSCLK >> ((__HCLKPRESC & 0x07)+1))
#else
#define __HCLK (__SYSCLK)
#endif
/*----------------------------------------------------------------------------
Define PCLK2
*----------------------------------------------------------------------------*/
#define __PCLK2PRESC ((__RCC_CFGR_VAL & CFGR_PRE2_MASK) >> 11)
#if (__PCLK2PRESC & 0x04)
#define __PCLK2 (__HCLK >> ((__PCLK2PRESC & 0x03)+1))
#else
#define __PCLK2 (__HCLK)
#endif
/*----------------------------------------------------------------------------
Define TIM1CLK
*----------------------------------------------------------------------------*/
#if (__PCLK2PRESC & 0x04)
#define __TIM1CLK (2*__PCLK2)
#else
#define __TIM1CLK (__PCLK2)
#endif
/*----------------------------------------------------------------------------
Define Timer PSC and ARR settings
*----------------------------------------------------------------------------*/
#define __VAL(__TIMCLK, __PERIOD) ((__TIMCLK/1000000UL)*__PERIOD)
//#define __PSC(__TIMCLK, __PERIOD) ((__VAL(__TIMCLK, __PERIOD)-1)>>15)
#define __PSC(__TIMCLK, __PERIOD) (((__VAL(__TIMCLK, __PERIOD)+49999UL)/50000UL) - 1)
#define __ARR(__TIMCLK, __PERIOD) ((__VAL(__TIMCLK, __PERIOD)/(__PSC(__TIMCLK, __PERIOD)+1)) - 1)
/*----------------------------------------------------------------------------
STM32 Timer setup.
initializes the Timer register
*----------------------------------------------------------------------------*/
void stm32_TimerSetup (void)
{
if (__TIMER_USED & 0x01) { // TIM1 used
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable clock for TIM1
TIM1->PSC = __PSC(__TIM1CLK, __TIM1_PERIOD); // set prescaler
TIM1->ARR = __ARR(__TIM1CLK, __TIM1_PERIOD); // set auto-reload
TIM1->RCR = __TIM1_RCR; // set repetition counter
TIM1->CR1 = 0; // reset command register 1
TIM1->CR2 = 0; // reset command register 2
if (__TIMER_DETAILS & 0x01) { // detailed settings used
TIM1->PSC = __TIM1_PSC; // set prescaler
TIM1->ARR = __TIM1_ARR; // set auto-reload
TIM1->CCR1 = __TIM1_CCR1; //
TIM1->CCR2 = __TIM1_CCR2; //
TIM1->CCR3 = __TIM1_CCR3; //
TIM1->CCR4 = __TIM1_CCR4; //
TIM1->CCMR1 = __TIM1_CCMR1; //
TIM1->CCMR2 = __TIM1_CCMR2; //
TIM1->CCER = __TIM1_CCER; // set capture/compare enable register
TIM1->SMCR = __TIM1_SMCR; // set slave mode control register
TIM1->CR1 = __TIM1_CR1; // set command register 1
TIM1->CR2 = __TIM1_CR2; // set command register 2
}
if (__TIMER_INTERRUPTS & 0x01) { // interrupts used
TIM1->DIER = __TIM1_DIER; // enable interrupt
NVIC->ISER[0] |= (1 << (TIM1_UP_IRQChannel & 0x1F)); // enable interrupt
}
TIM1->CR1 |= TIMX_CR1_CEN; // enable timer
} // end TIM1 used
} // end of stm32_TimSetup
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