mystm32_init.c

STM32 单片机例程

#include <stm32f10x_lib.h>                        // STM32F10x Library Definitions
#include "STM32_Reg.h"

//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------

//=========================================================================== Clock Configuration
// <e0> Clock Configuration
//   <h> Clock Control Register Configuration (RCC_CR)
//     <e1.24> PLLON: PLL enable         
//       <i> Default: PLL Disabled
//       <o2.18..21> PLLMUL: PLL Multiplication Factor
//         <i> Default: PLLSRC * 2
//                       <0=> PLLSRC * 2
//                       <1=> PLLSRC * 3
//                       <2=> PLLSRC * 4
//                       <3=> PLLSRC * 5
//                       <4=> PLLSRC * 6
//                       <5=> PLLSRC * 7
//                       <6=> PLLSRC * 8
//                       <7=> PLLSRC * 9
//                       <8=> PLLSRC * 10
//                       <9=> PLLSRC * 11
//                       <10=> PLLSRC * 12
//                       <11=> PLLSRC * 13
//                       <12=> PLLSRC * 14
//                       <13=> PLLSRC * 15
//                       <14=> PLLSRC * 16
//       <o2.17> PLLXTPRE: HSE divider for PLL entry
//         <i> Default: HSE
//                       <0=> HSE
//                       <1=> HSE / 2
//       <o2.16> PLLSRC: PLL entry clock source         
//         <i> Default: HSI/2
//                       <0=> HSI / 2
//                       <1=> HSE (PLLXTPRE output)
//     </e>
//     <o1.19> CSSON: Clock Security System enable
//       <i> Default: Clock detector OFF
//     <o1.18> HSEBYP: External High Speed clock Bypass
//       <i> Default: HSE oscillator not bypassed
//     <o1.16> HSEON: External High Speed clock enable 
//       <i> Default: HSE oscillator OFF
//     <o1.3..7> HSITRIM: Internal High Speed clock trimming  <0-31>
//       <i> Default: 0
//     <o1.0> HSION: Internal High Speed clock enable
//       <i> Default: internal 8MHz RC oscillator OFF
//   </h>
//   <h> Clock Configuration Register Configuration (RCC_CFGR)
//     <o2.24..26> MCO: Microcontroller Clock Output   
//       <i> Default: MCO = noClock
//                     <0=> MCO = noClock
//                     <4=> MCO = SYSCLK
//                     <5=> MCO = HSI
//                     <6=> MCO = HSE
//                     <7=> MCO = PLLCLK / 2
//     <o2.22> USBPRE: USB prescaler
//       <i> Default: USBCLK = PLLCLK / 1.5
//                     <0=> USBCLK = PLLCLK / 1.5
//                     <1=> USBCLK = PLLCLK
//     <o2.14..15> ADCPRE: ADC prescaler
//       <i> Default: ADCCLK=PCLK2 / 2
//                     <0=> ADCCLK = PCLK2 / 2
//                     <1=> ADCCLK = PCLK2 / 4
//                     <2=> ADCCLK = PCLK2 / 6
//                     <3=> ADCCLK = PCLK2 / 8
//     <o2.11..13> PPRE2: APB High speed prescaler (APB2)
//       <i> Default: PCLK2 = HCLK
//                     <0=> PCLK2 = HCLK
//                     <4=> PCLK2 = HCLK / 2 
//                     <5=> PCLK2 = HCLK / 4 
//                     <6=> PCLK2 = HCLK / 8 
//                     <7=> PCLK2 = HCLK / 16 
//     <o2.8..10> PPRE1: APB Low speed prescaler (APB1) 
//       <i> Default: PCLK1 = HCLK
//                     <0=> PCLK1 = HCLK
//                     <4=> PCLK1 = HCLK / 2 
//                     <5=> PCLK1 = HCLK / 4 
//                     <6=> PCLK1 = HCLK / 8 
//                     <7=> PCLK1 = HCLK / 16 
//     <o2.4..7> HPRE: AHB prescaler 
//       <i> Default: HCLK = SYSCLK
//                     <0=> HCLK = SYSCLK
//                     <8=> HCLK = SYSCLK / 2
//                     <9=> HCLK = SYSCLK / 4
//                     <10=> HCLK = SYSCLK / 8
//                     <11=> HCLK = SYSCLK / 16
//                     <12=> HCLK = SYSCLK / 64
//                     <13=> HCLK = SYSCLK / 128
//                     <14=> HCLK = SYSCLK / 256
//                     <15=> HCLK = SYSCLK / 512
//     <o2.0..1> SW: System Clock Switch
//       <i> Default: SYSCLK = HSE
//                     <0=> SYSCLK = HSI
//                     <1=> SYSCLK = HSE
//                     <2=> SYSCLK = PLLCLK
//   </h>
//   <o3>HSE: External High Speed Clock [Hz] <4000000-16000000>
//   <i> clock value for the used External High Speed Clock (4MHz <= HSE <= 16MHz).
//   <i> Default: 8000000  (8MHz)
// </e> End of Clock Configuration
#define __CLOCK_SETUP              1
#define __RCC_CR_VAL               0x01010082
#define __RCC_CFGR_VAL             0x001D8402
#define __HSE                      8000000

//=========================================================================== Independent Watchdog Configuration
// <e0> Independent Watchdog Configuration
//   <o1> IWDG period [us] <125-32000000:125>
//   <i> Set the timer period for Independent Watchdog.
//   <i> Default: 1000000  (1s)
// </e>

#define __IWDG_SETUP              0
#define __IWDG_PERIOD             0x000F4240

/*----------------------------------------------------------------------------
 Define  IWDG PR and RLR settings
 *----------------------------------------------------------------------------*/

#if   (__IWDG_PERIOD >  16384000UL)
  #define __IWDG_PR             (6)
  #define __IWDGCLOCK (32000UL/256)

#elif (__IWDG_PERIOD >   8192000UL)
  #define __IWDG_PR             (5)
  #define __IWDGCLOCK (32000UL/128)

//                       5000000
#elif (__IWDG_PERIOD >   4096000UL)
  #define __IWDG_PR             (4)
  #define __IWDGCLOCK  (32000UL/64)
#elif (__IWDG_PERIOD >   2048000UL)
  #define __IWDG_PR             (3)
  #define __IWDGCLOCK  (32000UL/32)
#elif (__IWDG_PERIOD >   1024000UL)
  #define __IWDG_PR             (2)
  #define __IWDGCLOCK  (32000UL/16)
#elif (__IWDG_PERIOD >    512000UL)
  #define __IWDG_PR             (1)
  #define __IWDGCLOCK   (32000UL/8)
#else
  #define __IWDG_PR             (0)
  #define __IWDGCLOCK   (32000UL/4)
#endif
#define __IWGDCLK  (32000UL/(0x04<<__IWDG_PR))
#define __IWDG_RLR (__IWDG_PERIOD*__IWGDCLK/1000000UL-1)


/*----------------------------------------------------------------------------
 Define  IWDG PR and RLR settings
 *----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
 STM32 Independent watchdog setup.
 initializes the IWDG register
 *----------------------------------------------------------------------------*/
void stm32_IwdgSetup (void) {

//  RCC->CSR |= (1<<0);                                           // LSI enable, necessary for IWDG
//  while ((RCC->CSR & (1<<1)) == 0);                             // wait till LSI is ready

  IWDG->KR  = 0x5555;                                           // enable write to PR, RLR
  IWDG->PR  = __IWDG_PR;                                        // Init prescaler
  IWDG->RLR = __IWDG_RLR;                                       // Init RLR
  IWDG->KR  = 0xAAA1;                                           // Reload the watchdog
  IWDG->KR  = 0xCCCC;                                           // Start the watchdog
} // end of stm32_IwdgSetup

//定义长延时喂狗5s
#define __LongIWDG_PERIOD         5000000UL
#define __LongIWDG_PR             (4)
#define __LongIWDGCLOCK   (32000UL/64)
#define __LongIWGDCLK  (32000UL/(0x04<<__LongIWDG_PR))
#define __LongIWDG_RLR (__LongIWDG_PERIOD*__LongIWGDCLK/1000000UL-1)

void stm32_IwdgSetupLong (void) {

//  RCC->CSR |= (1<<0);                                           // LSI enable, necessary for IWDG
//  while ((RCC->CSR & (1<<1)) == 0);                             // wait till LSI is ready

  IWDG->KR  = 0x5555;                                           // enable write to PR, RLR
  IWDG->PR  = __LongIWDG_PR;                                        // Init prescaler
  IWDG->RLR = __LongIWDG_RLR;                                       // Init RLR
  IWDG->KR  = 0xAAA1;                                           // Reload the watchdog
  IWDG->KR  = 0xCCCC;                                           // Start the watchdog
} // end of stm32_IwdgSetup

//定义短延时喂狗100ms
#define __ShortIWDG_PERIOD         100000UL
#define __ShortIWDG_PR             (0)
#define __ShortIWDGCLOCK   (32000UL/64)
#define __ShortIWGDCLK  (32000UL/(0x04<<__ShortIWDG_PR))
#define __ShortIWDG_RLR (__ShortIWDG_PERIOD*__ShortIWGDCLK/1000000UL-1)

void stm32_IwdgSetupShort (void) {

//  RCC->CSR |= (1<<0);                                           // LSI enable, necessary for IWDG
//  while ((RCC->CSR & (1<<1)) == 0);                             // wait till LSI is ready

  IWDG->KR  = 0x5555;                                           // enable write to PR, RLR
  IWDG->PR  = __ShortIWDG_PR;                                        // Init prescaler
  IWDG->RLR = __ShortIWDG_RLR;                                       // Init RLR
  IWDG->KR  = 0xAAA1;                                           // Reload the watchdog
  IWDG->KR  = 0xCCCC;                                           // Start the watchdog
} // end of stm32_IwdgSetup

//=========================================================================== Timer Configuration
// <e0> Timer Configuration
//--------------------------------------------------------------------------- Timer 1 enabled
//   <e1.0> TIM1 : Timer 1 enabled
//     <o4> TIM1 period [us] <1-72000000:10>
//       <i> Set the timer period for Timer 1.
//       <i> Default: 1000  (1ms)
//       <i> Ignored if detailed settings is selected
//     <o7> TIM1 repetition counter <0-255>
//       <i> Set the repetition counter for Timer 1.
//       <i> Default: 0
//       <i> Ignored if detailed settings is selected
//     <e2.0> TIM1 detailed settings
//--------------------------------------------------------------------------- Timer 1 detailed settings
//       <o5> TIM1.PSC: Timer1 Prescaler <0-65535>
//         <i> Set the prescaler for Timer 1.
//       <o6> TIM1.ARR: Timer1 Auto-reload <0-65535>
//         <i> Set the Auto-reload for Timer 1.
//       <o7> TIM1.RCR: Timer1 Repetition Counter <0-255>
//         <i> Set the Repetition Counter for Timer 1.
//
//       <h> Timer 1 Control Register 1 Configuration (TIM1_CR1)
//         <o8.8..9> TIM1_CR1.CKD: Clock division   
//           <i> Default: tDTS = tCK_INT
//           <i> devision ratio between timer clock and dead time
//                     <0=> tDTS = tCK_INT
//                     <1=> tDTS = 2*tCK_INT
//                     <2=> tDTS = 4*tCK_INT
//         <o8.7> TIM1_CR1.ARPE: Auto-reload preload enable
//           <i> Default: Auto-reload preload disenabled
//         <o8.5..6> TIM1_CR1.CMS: Center aligned mode selection   
//           <i> Default: Edge-aligned
//                     <0=> Edge-aligned
//                     <1=> Center-aligned mode1
//                     <2=> Center-aligned mode2
//                     <3=> Center-aligned mode3
//         <o8.4> TIM1_CR1.DIR: Direction
//           <i> Default: DIR = Counter used as up-counter
//           <i> read only if timer is configured as Center-aligned or Encoder mode   
//                     <0=> Counter used as up-counter
//                     <1=> Counter used as down-counter
//         <o8.3> TIM1_CR1.OPM: One pulse mode enable
//           <i> Default: One pulse mode disabled
//         <o8.2> TIM1_CR1.URS: Update request source   
//           <i> Default: URS = Counter over-/underflow, UG bit, Slave mode controller
//                     <0=> Counter over-/underflow, UG bit, Slave mode controller
//                     <1=> Counter over-/underflow
//         <o8.1> TIM1_CR1.UDIS: Update disable
//           <i> Default: Update enabled
//       </h>
//
//       <h> Timer 1 Control Register 2 Configuration (TIM1_CR2)
//         <o9.14> TIM1_CR2.OIS4: Output Idle state4 (OC4 output)   <0-1>
//         <o9.13> TIM1_CR2.OIS3N: Output Idle state3 (OC3N output) <0-1>
//         <o9.12> TIM1_CR2.OIS3: Output Idle state3 (OC3 output)   <0-1>
//         <o9.11> TIM1_CR2.OIS2N: Output Idle state2 (OC2N output) <0-1> 
//         <o9.10> TIM1_CR2.OIS2: Output Idle state2 (OC2 output)   <0-1>
//         <o9.9> TIM1_CR2.OIS1N: Output Idle state1 (OC1N output)
//           <i> Default: OC1 = 0
//                     <0=> OC1N=0 when MOE=0
//                     <1=> OC1N=1 when MOE=0
//         <o9.8> TIM1_CR2.OI1S: Output Idle state1 (OC1 output)  
//           <i> Default: OC1=0
//                     <0=> OC1=0 when MOE=0
//                     <1=> OC1=1 when MOE=0
//         <o9.7> TIM1_CR2.TI1S: TI1 Selection  
//           <i> Default: TIM1CH1 connected to TI1 input
//                     <0=> TIM1CH1 connected to TI1 input
//                     <1=> TIM1CH1,CH2,CH3 connected to TI1 input
//         <o9.4..6> TIM1_CR2.MMS: Master Mode Selection  
//           <i> Default: Reset
//           <i> Select information to be sent in master mode to slave timers for synchronisation
//                     <0=> Reset
//                     <1=> Enable
//                     <2=> Update
//                     <3=> Compare Pulse
//                     <4=> Compare OC1REF iused as TRGO