📄 mystm32_init.c
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//
//--------------------------------------------------------------------------- Timer 1 channel 1
// <h> Channel 1 Configuration
// <h> Cannel configured as output
// <o11.7> TIM1_CCMR1.OC1CE: Output Compare 1 Clear enabled
// <o11.4..6> TIM1_CCMR1.OC1M: Output Compare 1 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 1 to active level on match
// <2=> Set channel 1 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o11.3> TIM1_CCMR1.OC1PE: Output Compare 1 Preload enabled
// <o11.2> TIM1_CCMR1.OC1FE: Output Compare 1 Fast enabled
// <o11.0..1> TIM1_CCMR1.CC1S: Capture/compare 1 selection
// <i> Default: CC1 configured as output
// <0=> CC1 configured as output
// <o13.3> TIM1_CCER.CC1NP: Capture/compare 1 Complementary output Polarity set
// <i> Default: OC1N active high
// <0=> OC1N active high
// <1=> OC1N active low
// <o13.2> TIM1_CCER.CC1NE: Capture/compare 1 Complementary output enabled
// <i> Default: OC1N not active
// <0=> OC1N not active
// <1=> OC1N is output on corresponding pin
// <o13.1> TIM1_CCER.CC1P: Capture/compare 1 output Polarity set
// <i> Default: OC1 active high
// <0=> OC1 active high
// <1=> OC1 active low
// <o13.0> TIM1_CCER.CC1E: Capture/compare 1 output enabled
// <i> Default: OC1 not active
// <0=> OC1 not active
// <1=> OC1 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o11.4..7> TIM1_CCMR1.IC1F: Input Capture 1 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o11.2..3> TIM1_CCMR1.IC1PSC: Input Capture 1 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o11.0..1> TIM1_CCMR1.CC1S: Capture/compare 1 selection
// <i> Default: CC1 configured as output
// <0=> CC1 configured as output
// <1=> CC1 configured as input, IC1 mapped on TI1
// <2=> CC1 configured as input, IC1 mapped on TI2
// <3=> CC1 configured as input, IC1 mapped on TRGI
// <o13.1> TIM1_CCER.CC1P: Capture/compare 1 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.0> TIM1_CCER.CC1E: Capture/compare 1 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o14> TIM1_CCR1: Capture/compare register 1 <0-65535>
// <i> Set the Compare register value for compare register 1.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 2
// <h> Channel 2 Configuration
// <h> Cannel configured as output
// <o11.15> TIM1_CCMR1.OC2CE: Output Compare 2 Clear enabled
// <o11.12..14> TIM1_CCMR1.OC2M: Output Compare 2 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 2 to active level on match
// <2=> Set channel 2 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o11.11> TIM1_CCMR1.OC2PE: Output Compare 2 Preload enabled
// <o11.10> TIM1_CCMR1.OC2FE: Output Compare 2 Fast enabled
// <o11.8..9> TIM1_CCMR1.CC2S: Capture/compare 2 selection
// <i> Default: CC2 configured as output
// <0=> CC2 configured as output
// <o13.7> TIM1_CCER.CC2NP: Capture/compare 2 Complementary output Polarity set
// <i> Default: OC2N active high
// <0=> OC2N active high
// <1=> OC2N active low
// <o13.6> TIM1_CCER.CC2NE: Capture/compare 2 Complementary output enabled
// <i> Default: OC2N not active
// <0=> OC2N not active
// <1=> OC2N is output on corresponding pin
// <o13.5> TIM1_CCER.CC2P: Capture/compare 2 output Polarity set
// <i> Default: OC2 active high
// <0=> OC2 active high
// <1=> OC2 active low
// <o13.4> TIM1_CCER.CC2E: Capture/compare 2 output enabled
// <i> Default: OC2 not active
// <0=> OC2 not active
// <1=> OC2 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o11.12..15> TIM1_CCMR1.IC2F: Input Capture 2 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o11.10..11> TIM1_CCMR1.IC2PSC: Input Capture 2 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o11.8..9> TIM1_CCMR1.CC2S: Capture/compare 2 selection
// <i> Default: CC2 configured as output
// <0=> CC2 configured as output
// <1=> CC2 configured as input, IC2 mapped on TI2
// <2=> CC2 configured as input, IC2 mapped on TI1
// <3=> CC2 configured as input, IC2 mapped on TRGI
// <o13.5> TIM1_CCER.CC2P: Capture/compare 2 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.4> TIM1_CCER.CC2E: Capture/compare 2 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o15> TIM1_CCR2: Capture/compare register 2 <0-65535>
// <i> Set the Compare register value for compare register 2.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 3
// <h> Channel 3 Configuration
// <h> Cannel configured as output
// <o12.7> TIM1_CCMR2.OC3CE: Output Compare 3 Clear enabled
// <o12.4..6> TIM1_CCMR2.OC3M: Output Compare 3 Mode
// <i> Default: Frozen
// <0=> Frozen
// <1=> Set channel 3 to active level on match
// <2=> Set channel 3 to inactive level on match
// <3=> Toggle
// <4=> Force inactive level
// <5=> Force active level
// <6=> PWM mode 1
// <7=> PWM mode 2
// <o12.3> TIM1_CCMR2.OC3PE: Output Compare 3 Preload enabled
// <o12.2> TIM1_CCMR2.OC3FE: Output Compare 3 Fast enabled
// <o12.0..1> TIM1_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <o13.11> TIM1_CCER.CC3NP: Capture/compare 3 Complementary output Polarity set
// <i> Default: OC3N active high
// <0=> OC3N active high
// <1=> OC3N active low
// <o13.10> TIM1_CCER.CC3NE: Capture/compare 3 Complementary output enabled
// <i> Default: OC3N not active
// <0=> OC3N not active
// <1=> OC3N is output on corresponding pin
// <o13.9> TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: OC3 active high
// <0=> OC3 active high
// <1=> OC3 active low
// <o13.8> TIM1_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: OC3 not active
// <0=> OC3 not active
// <1=> OC3 is output on corresponding pin
// </h>
// <h> Channel configured as input
// <o12.4..7> TIM1_CCMR2.IC3F: Input Capture 3 Filter
// <i> Default: No filter
// <0=> No filter
// <1=> fSampling=fCK_INT, N=2
// <2=> fSampling=fCK_INT, N=4
// <3=> fSampling=fCK_INT, N=8
// <4=> fSampling=fDTS/2, N=6
// <5=> fSampling=fDTS/2, N=8
// <6=> fSampling=fDTS/4, N=6
// <7=> fSampling=fDTS/4, N=8
// <8=> fSampling=fDTS/8, N=6
// <9=> fSampling=fDTS/8, N=8
// <10=> fSampling=fDTS/16, N=5
// <11=> fSampling=fDTS/16, N=6
// <12=> fSampling=fDTS/16, N=8
// <13=> fSampling=fDTS/32, N=5
// <14=> fSampling=fDTS/32, N=6
// <15=> fSampling=fDTS/32, N=8
// <o12.2..3> TIM1_CCMR2.IC3PSC: Input Capture 3 Prescaler
// <i> Default: No prescaler
// <0=> No prescaler
// <1=> capture every 2 events
// <2=> capture every 4 events
// <3=> capture every 8 events
// <o12.0..1> TIM1_CCMR2.CC3S: Capture/compare 3 selection
// <i> Default: CC3 configured as output
// <0=> CC3 configured as output
// <1=> CC3 configured as input, IC3 mapped on TI3
// <2=> CC3 configured as input, IC3 mapped on TI4
// <3=> CC3 configured as input, IC3 mapped on TRGI
// <o13.9> TIM1_CCER.CC3P: Capture/compare 3 output Polarity set
// <i> Default: non-inverted
// <0=> non-inverted
// <1=> inverted
// <o13.8> TIM1_CCER.CC3E: Capture/compare 3 output enabled
// <i> Default: Capture disabled
// <0=> Capture disabled
// <1=> Capture enabled
// </h>
// <o16> TIM1_CCR3: Capture/compare register 3 <0-65535>
// <i> Set the Compare register value for compare register 3.
// <i> Default: 0
// </h>
//
//--------------------------------------------------------------------------- Timer 1 channel 4
// <h> Channel 4 Configuration
// <h> Cannel configured as output
// <o12.15> TIM1_CCMR2.OC4CE: Output Compare 4 Clear enabled
// <o12.12..14> TIM1_CCMR2.OC4M: Output Compare 4 Mode
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