start-pxa250.s

PXA250上的XBOOT

;
; $Id: start-pxa250.s,v 1.4 2003/09/24 12:13:35 jfabo Exp $
;
; Copyright (C) 2001, 2002 ETC s.r.o.
;
; This program is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License
; as published by the Free Software Foundation; either version 2
; of the License, or (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
; 02111-1307, USA.
;
; Written by Marcel Telka <[e-mail]>, 2001, 2002.
;
; Documentation:
; [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
;     Developer's Manual", February 2002, Order Number: 278522-001
; [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
;     Revision 1.0, February 2002
; [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
;     Revision 1.0, February 2002
;

	INCLUDE boardasm.h

	IF CPU = "PXA250"

	INCLUDE kxarm.h

FLD_OFFSET	EQU	0x1C000
RAMIMAGE_OFFSET	EQU	0x00000
RAMIMAGE_SIZE	EQU	0xC000
STACK_OFFSET	EQU	0x14000

; this code is executed on HW/SW reset (pc=0x00xxxxxx),
; after relocation (pc=0xA0xxxxxx)
; or after initializing MMU (pc=0x8Cxxxxxx) (in progress)
; FIXME: jump to StartUp after init MMU

	STARTUPTEXT

	EXPORT	StartUp
StartUp
; check Flash or RAM execution
	ands	r0, pc, #0xFF000000
	bne	SkipLLSetup	; skipping low level setup

; clear RDH & PH bits in PSSR
	mov	r1, #0x40000000
	add	r1, r1, #0x00F00000
	mov	r2, #0x30
	str	r2, [r1, #4]

	; setup processor speed
	ldr	r0, =0x41300000			; CM_BASE
	ldr	r1, =0x141			; CCCR_N_1_0 | CCCR_M_2 | CCCR_L_27 = 200 MHz
	str	r1, [r0, #0x0]			; CCCR_OFFSET

	mov	r1, #3				; FCS = 1, TURBO = 1
	mcr	p14, 0, r1, c6, c0, 0		; change frequency

	; setup memory - see 6.12 in [1]

	; step 1 - wait 200 us
	mov	r0,#0x2700      		; wait 200 us @ 99.5 MHz
1	subs	r0, r0, #1
	bne	%b1
	; TODO: complete step 1 for Synchronous Static memory

	ldr	r0, =0x48000000			; MC_BASE

	; step 1.a - setup MSCx
	ldr	r1, =0x000012B3			; MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3)
	str	r1, [r0, #0x8]			; MSC0_OFFSET

	; step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
	; see AUTO REFRESH chapter in section D. in [2] and in [3]
	; DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
	; DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
	; TODO: complete for Synchronous Static memory
	ldr	r1, [r0, #4]			; MDREFR_OFFSET
	ldr	r2, =0x01000FFF			; MDREFR_K1FREE | MDREFR_DRI_MASK
	bic	r1, r1, r2
		IF CONFIG_EP250_K4S281633 != ""
	orr	r1, r1, #48			; MDREFR_DRI(48)
		ENDIF
		IF CONFIG_EP250_K4S561633 != ""
	orr	r1, r1, #24			; MDREFR_DRI(24)
		ENDIF
	str	r1, [r0, #4]			; MDREFR_OFFSET

	; step 2 - only for Synchronous Static memory (TODO)

	; step 3 - same as step 4

	; step 4

	; step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
	orr	r1, r1, #0x00010000		; MDREFR_K1RUN
	bic	r1, r1, #0x00020000		; MDREFR_K1DB2
	str	r1, [r0, #4]			; MDREFR_OFFSET

	; step 4.b - clear MDREFR:SLFRSH
	bic	r1, r1, #0x00400000		; MDREFR_SLFRSH
	str	r1, [r0, #4]			; MDREFR_OFFSET

	; step 4.c - set MDREFR:E1PIN
	orr	r1, r1, #0x00008000		; MDREFR_E1PIN
	str	r1, [r0, #4]			; MDREFR_OFFSET

	; step 4.d - automatically done

	; steps 4.e and 4.f - configure SDRAM
		IF CONFIG_EP250_K4S281633 != ""
	ldr	r1, =0x00000AA8			; MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0
		ENDIF
		IF CONFIG_EP250_K4S561633 != ""
	ldr	r1, =0x00000AC8			; MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0
		ENDIF
	str	r1, [r0, #0]			; MDCNFG_OFFSET

	; step 5 - wait at least 200 us for SDRAM
	; see section B. in [2]
	mov	r2,#0x2700      		; wait 200 us @ 99.5 MHz
1	subs	r2, r2, #1
	bne	%b1

	; step 6 - after reset dcache is disabled, so automatically done

	; step 7 - eight refresh cycles
	mov	r2, #0xA0000000
	ldr	r3, [r2]
	ldr	r3, [r2]
	ldr	r3, [r2]
	ldr	r3, [r2]
	ldr	r3, [r2]
	ldr	r3, [r2]
	ldr	r3, [r2]
	ldr	r3, [r2]

	; step 8 - we don't need dcache now

	; step 9 - enable SDRAM partition 0
	orr	r1, r1, #1			; MDCNFG_DE0
	str	r1, [r0, #0]			; MDCNFG_OFFSET

	; step 10 - write MDMRS
	mov	r1, #0
	str	r1, [r0, #0x40]			; MDMRS_OFFSET

	; step 11 - optional (TODO)

; setup stack
	ldr	sp, =0xA0000000 + STACK_OFFSET

; relocate image
	ldr	r0, =0xA0000000 + RAMIMAGE_OFFSET	; dest (RAM)
	mov	r1, #0x00000000				; src (Flash)
	mov	r2, #RAMIMAGE_SIZE			; count (32 kB)
	mov	r4, r0					; save dest
	IMPORT	memcpy
	bl	memcpy

; jump to StartUp
	mov	pc, r4

SkipLLSetup
; create translation page table
	ldr	r0, =0xA0000000	+ FLD_OFFSET	; TTB address
	mov	r4, r0				; save TTB address
	IMPORT	OEMAddressTable
	ldr	r1, =OEMAddressTable
	ldr	r2, =StartUp - 0x1000
	sub	r1, r1, r2
	IMPORT	CreatePageTables
	bl	CreatePageTables

; initialize & enable MMU
	mcr	p15, 0, r4, c2, c0, 0
	mov	r0, #0x0
	mov	r1, #0x1
	mcr	p15, 0, r1, c3, c0, 0
	mcr	p15, 0, r0, c8, c7, 0
	mrc	p15, 0, r1, c1, c0, 0

	ldr	r0, =VirtualStart

	orr	r1, r1, #0x1
	nop
	mcr	p15, 0, r1, c1, c0, 0
	mov	pc, r0
	nop

VirtualStart
; setup stack
	ldr	sp, =0x8C000000 + STACK_OFFSET
	
	IMPORT	main
	b	main

; Launch is needed by xboot (main) for jumping to downloaded image,
; target physical address (LaunchAddr) is in r0
	EXPORT	Launch
Launch
	ldr	r2, =PhysicalStart
	mov	r3, #0x14000000
	add	r2, r2, r3	; convert PhysicalStart to physical address
	
	mov	r1, #0x0070	; disable MMU
	mcr	p15, 0, r1, c1, c0, 0

	nop
	mov	pc, r2		; jump to PhysicalStart
	nop

PhysicalStart
	mov	r2, #0x0
	mcr	p15, 0, r2, c8, c7, 0	; flush TLBs (I + D)
	mov	pc, r0

	ENDIF

	END