📄 bldc.lst
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775 00b6 8b8b MAR * ,AR3
776 00b7 9080 SACL *
777 .line 63
778 ;>>>> EVAIFRA = 0XFFFF; /* Clear all Group A interrupt flags */
779 00b8 7802 ADRK 2
780 00b9 aea0 SPLK #-1,*+
00ba ffff
781 .line 64
782 ;>>>> EVAIFRB = 0XFFFF; /* Clear all Group B interrupt flags */
783 00bb aea0 SPLK #-1,*+
00bc ffff
784 .line 65
785 ;>>>> EVAIFRC = 0XFFFF; /* Clear all Group C interrupt flags */
786 ;>>>> #if (REAL_TIME==TRUE)
787 00bd ae8c SPLK #-1,* ,AR4
00be ffff
788 .line 68
789 ;>>>> IMR = 0X0044; /* En Int lvl 3 & 7 (T2 ISR) */
790 ;>>>> #endif /* (REAL_TIME==TRUE) */
791 ;>>>> #if (REAL_TIME==FALSE)
792 ;>>>> IMR = 0X0004; /* En Int lvl 3 (T2 ISR) */
793 ;>>>> #endif /* (REAL_TIME==TRUE)*/
794 ;>>>> #endif /* (TARGET==F2407) */
795 00bf b404 LARK AR4,4
796 00c0 b944 LACK 68
797 00c1 9089 SACL * ,AR1
798 00c2 EPI0_3:
799 .line 77
800 00c2 7c02 SBRK 2
801 00c3 0090 LAR AR0,*-
802 00c4 7680 PSHD *
803 00c5 ef00 RET
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 18
804
805 .endfunc 471,000000000H,1
806
807 .sym _phantom,_phantom,32,2,0
808 .globl _phantom
809
810 .func 474
811 ;>>>> void interrupt phantom(void)
812 ;>>>> static int phantom_count;
813 ******************************************************
814 * FUNCTION DEF : _phantom
815 ******************************************************
816 00c6 _phantom:
817 00c6 7a80 CALL I$$SAVE
00c7 0000!
818 00c8 8180 SAR AR1,*
819 00c9 b001 LARK AR0,1
820 00ca 00e0 LAR AR0,*0+
821
822
823 .sym _phantom_count,_phantom_count$1,4,3,16
824 .line 5
825 ;>>>> phantom_count ++;
826 00cb bc00- LDPK _phantom_count$1
827 00cc 1056- LAC _phantom_count$1
828 00cd b801 ADDK 1
829 00ce 9056- SACL _phantom_count$1
830 00cf EPI0_4:
831 .line 15
832 00cf 7c01 SBRK 1
833 00d0 7989 B I$$REST,AR1 ;and return
00d1 0000!
834
835 .endfunc 488,000000000H,1
836
837 .sym _rtmon_init,_rtmon_init,32,2,0
838 .globl _rtmon_init
839
840 .func 494
841 ;>>>> void rtmon_init(void)
842 ******************************************************
843 * FUNCTION DEF : _rtmon_init
844 ******************************************************
845 00d2 _rtmon_init:
846 00d2 8aa0 POPD *+
847 00d3 80a0 SAR AR0,*+
848 00d4 8180 SAR AR1,*
849 00d5 b001 LARK AR0,1
850 00d6 00e0 LAR AR0,*0+
851
852 .line 3
853 ;>>>> asm(" CALL MON_RT_CNFG ");
854 00d7 7a80 CALL MON_RT_CNFG
00d8 0000!
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 19
855 00d9 EPI0_5:
856 .line 4
857 00d9 7c02 SBRK 2
858 00da 0090 LAR AR0,*-
859 00db 7680 PSHD *
860 00dc ef00 RET
861
862 .endfunc 497,000000000H,1
863
864 .sym _time_base_init,_time_base_init,32,2,0
865 .globl _time_base_init
866
867 .func 504
868 ;>>>> void time_base_init(void)
869 ******************************************************
870 * FUNCTION DEF : _time_base_init
871 ******************************************************
872 00dd _time_base_init:
873 00dd 8aa0 POPD *+
874 00de 80a0 SAR AR0,*+
875 00df 8180 SAR AR1,*
876 00e0 b001 LARK AR0,1
877 00e1 00eb LAR AR0,*0+,AR3
878
879 .line 3
880 ;>>>> T2PR = SYSTEM_INT_PERIOD; /* Initialize period register */
881 00e2 bf0b LARK AR3,29703
00e3 7407
882 00e4 aea0 SPLK #1000,*+
00e5 03e8
883 .line 10
884 ;>>>> T2CON = 0x9040;
885 00e6 ae89 SPLK #-28608,* ,AR1
00e7 9040
886 00e8 EPI0_6:
887 .line 12
888 00e8 7c02 SBRK 2
889 00e9 0090 LAR AR0,*-
890 00ea 7680 PSHD *
891 00eb ef00 RET
892
893 .endfunc 515,000000000H,1
894
895 .sym _evm_pwm_init,_evm_pwm_init,32,2,0
896 .globl _evm_pwm_init
897
898 .func 517
899 ;>>>> void evm_pwm_init(void)
900 ******************************************************
901 * FUNCTION DEF : _evm_pwm_init
902 ******************************************************
903 00ec _evm_pwm_init:
904 00ec 8aa0 POPD *+
905 00ed 80a0 SAR AR0,*+
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 20
906 00ee 8180 SAR AR1,*
907 00ef b001 LARK AR0,1
908 00f0 00eb LAR AR0,*0+,AR3
909
910 .line 3
911 ;>>>> MCRA = MCRA & 0XBFFF; /* Select Secondary function IOPB6 */
912 00f1 bf0b LARK AR3,28816
00f2 7090
913 00f3 bf80 LACK 49151
00f4 bfff
914 00f5 6e80 AND *
915 00f6 9080 SACL *
916 .line 4
917 ;>>>> PBDATDIR = PBDATDIR |0X4000; /* Set IOPB6 as output */
918 00f7 bf80 LACK 16384
00f8 4000
919 00f9 780a ADRK 10
920 00fa 6d80 OR *
921 00fb 9080 SACL *
922 .line 5
923 ;>>>> PBDATDIR = PBDATDIR & EVM_IOPB6; /* Set IOPB6 low/high, Enable/disable PWM */
924 00fc bf80 LACK 65471
00fd ffbf
925 00fe 6e80 AND *
926 00ff 9089 SACL * ,AR1
927 0100 EPI0_7:
928 .line 6
929 0100 7c02 SBRK 2
930 0101 0090 LAR AR0,*-
931 0102 7680 PSHD *
932 0103 ef00 RET
933
934 .endfunc 522,000000000H,1
935
936 .sym _update_v_timer,_update_v_timer,32,2,0
937 .globl _update_v_timer
938
939 .func 524
940 ;>>>> void update_v_timer(void)
941 ******************************************************
942 * FUNCTION DEF : _update_v_timer
943 ******************************************************
944 0104 _update_v_timer:
945 0104 8aa0 POPD *+
946 0105 80a0 SAR AR0,*+
947 0106 8180 SAR AR1,*
948 0107 b001 LARK AR0,1
949 0108 00e0 LAR AR0,*0+
950
951 .line 3
952 ;>>>> bldc.cmtn.v_timer++; /* Inc virtual timer */
953 0109 bc00- LDPK _bldc+33
954 010a 1038- LAC _bldc+33
955 010b b801 ADDK 1
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 21
956 010c 9038- SACL _bldc+33
957 .line 4
958 ;>>>> bldc.cmtn.v_timer = bldc.cmtn.v_timer & 0x7fff; /* Force 15 bit wrap around and save */
959 010d bfb0 ANDK 32767
010e 7fff
960 010f 9038- SACL _bldc+33
961 0110 EPI0_8:
962 .line 5
963 0110 7c02 SBRK 2
964 0111 0090 LAR AR0,*-
965 0112 7680 PSHD *
966 0113 ef00 RET
967
968 .endfunc 528,000000000H,1
969
970 .sym _isr_ticker,_isr_ticker,4,2,16
971 .globl _isr_ticker
972 *****************************************************
973 * UNDEFINED REFERENCES *
974 *****************************************************
975 .global _enable_ints
976 .global I$$SAVE
977 .global I$$REST
978 .global _disable_ints
979 .end
No Errors, No Warnings
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