📄 bldc.lst
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005c 0079'
568 005d L3:
569 .line 30
570 ;>>>> bldc.align_flag = 0;
571 ;>>>> #if (BUILDLEVEL==LEVEL1)
572 005d b900 LACK 0
573 005e 901e- SACL _bldc+7
574 005f L2:
575 .line 34
576 ;>>>> BLDC_TI_Run(&bldc);
577 005f bf80 LALK _bldc+0
0060 0017-
578 0061 8b89 MAR * ,AR1
579 0062 90a0 SACL *+
580 0063 7a80 CALL _BLDC_TI_Run
0064 0000!
581 0065 8b90 MAR *-
582 .line 36
583 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
584 0066 bc00- LDPK _bldc+13
585 0067 a924- BLDD _bldc+13,#_pwm
0068 0006-
586 .line 38
587 ;>>>> pwm.update(&pwm);
588 ;>>>> #endif /* (BUILDLEVEL==LEVEL1) */
589 ;>>>> #if (BUILDLEVEL==LEVEL2)
590 ;>>>> bldc.cmtn.va = adc.c1_out;
591 ;>>>> bldc.cmtn.vb = adc.c2_out;
592 ;>>>> bldc.cmtn.vc = adc.c3_out;
593 ;>>>> BLDC_TI_Run(&bldc);
594 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
595 ;>>>> pwm.update(&pwm);
596 ;>>>> adc.update(&adc);
597 ;>>>> #endif /* (BUILDLEVEL==LEVEL2) */
598 ;>>>> #if (BUILDLEVEL==LEVEL3)
599 ;>>>> bldc.cmtn.va = adc.c1_out;
600 ;>>>> bldc.cmtn.vb = adc.c2_out;
601 ;>>>> bldc.cmtn.vc = adc.c3_out;
602 ;>>>> BLDC_TI_Run(&bldc);
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 14
603 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
604 ;>>>> pwm.update(&pwm);
605 ;>>>> adc.update(&adc);
606 ;>>>> #endif /* (BUILDLEVEL==LEVEL3) */
607 ;>>>> #if (BUILDLEVEL==LEVEL4)
608 ;>>>> bldc.cmtn.va = adc.c1_out;
609 ;>>>> bldc.cmtn.vb = adc.c2_out;
610 ;>>>> bldc.cmtn.vc = adc.c3_out;
611 ;>>>> BLDC_TI_Run(&bldc);
612 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
613 ;>>>> pwm.d_func = bldc.rmp2.out;
614 ;>>>> pwm.update(&pwm);
615 ;>>>> adc.update(&adc);
616 ;>>>> #endif /* (BUILDLEVEL==LEVEL4) */
617 ;>>>> #if (BUILDLEVEL==LEVEL5)
618 ;>>>> bldc.cmtn.va = adc.c1_out;
619 ;>>>> bldc.cmtn.vb = adc.c2_out;
620 ;>>>> bldc.cmtn.vc = adc.c3_out;
621 ;>>>> bldc.pid2.fb_reg2 = adc.c4_out;
622 ;>>>> BLDC_TI_Run(&bldc);
623 ;>>>> if(FALSE == bldc.I_loop_flg)
624 ;>>>> pwm.d_func = bldc.rmp2.out;
625 ;>>>> else
626 ;>>>> pwm.d_func = bldc.pid2.out_reg2;
627 ;>>>> pwm.cmtn_ptr_bd = bldc.mod6.cntr; /* Input to PWM driver */
628 ;>>>> pwm.update(&pwm);
629 ;>>>> adc.update(&adc);
630 ;>>>> #endif /* (BUILDLEVEL==LEVEL5) */
631 0069 bf80 LALK _pwm+0
006a 0006-
632 006b 90a0 SACL *+
633 006c 100b- LAC _pwm+5
634 006d be30 CALA
635 006e 8b90 MAR *-
636 .line 114
637 ;>>>> update_v_timer();
638 006f 7a80 CALL _update_v_timer
0070 0104'
639 .line 115
640 ;>>>> dac.update(&dac);
641 0071 bf80 LALK _dac+0
0072 0000-
642 0073 90a0 SACL *+
643 0074 bc00- LDPK _dac+5
644 0075 1005- LAC _dac+5
645 0076 be30 CALA
646 0077 8b90 MAR *-
647 .line 117
648 ;>>>> asm(" SETC XF ");
649 0078 be4d SETC XF
650 0079 EPI0_2:
651 .line 120
652 0079 7c01 SBRK 1
653 007a 7989 B I$$REST,AR1 ;and return
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 15
007b 0000!
654
655 .endfunc 392,000000000H,1
656
657 .sym _RstSystem,_RstSystem,32,2,0
658 .globl _RstSystem
659
660 .func 395
661 ;>>>> void RstSystem(void)
662 ;>>>> #if (TARGET==F243)
663 ;>>>> disable_ints(); /* Make sure the interrupts are disabled */
664 ;>>>> IMR = 0x00; /* Mask all interrupts */
665 ;>>>> IFR = 0x00ff; /* Clear any pending interrupts, if any */
666 ;>>>> PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
667 ;>>>> EVIFRA = EVIFRA | 0x0001; /* Clear PDP int flag */
668 ;>>>> asm(" CLRC SXM "); /* Clear signextension mode */
669 ;>>>> asm(" CLRC OVM "); /* Reset overflow mode */
670 ;>>>> asm(" CLRC CNF "); /* Config block B0 to data memory */
671 ;>>>> asm(" SPM 0 "); /* Set product mode at 0 */
672 ;>>>> WSGR=WAIT_STATES; /* Initialize Wait State Generator */
673 ;>>>> SCSR=0x40c0; /* Init SCSR */
674 ;>>>> wdog.disable(); /* Vccp/Wddis pin/bit must be high */
675 ;>>>> wdog.reset(); /* reset watchdog counter */
676 ;>>>> EVIMRB=0x0004; /* Enable the timer2 underflow interrupt */
677 ;>>>> EVIFRA = 0xFFFF; /* Clear all Group A interrupt flags */
678 ;>>>> EVIFRB = 0xFFFF; /* Clear all Group B interrupt flags */
679 ;>>>> EVIFRC = 0xFFFF; /* Clear all Group C interrupt flags */
680 ;>>>> #if (REAL_TIME==TRUE)
681 ;>>>> IMR = 0x0044; /* En Int lvl 3 & 7 (T2 ISR) */
682 ;>>>> #endif /* (REAL_TIME==TRUE) */
683 ;>>>> #if (REAL_TIME==FALSE)
684 ;>>>> IMR = 0x0004; /* En Int lvl 3 (T2 ISR) */
685 ;>>>> #endif /* (REAL_TIME==TRUE)*/
686 ;>>>> #endif /* (TARGET==F243) */
687 ;>>>> #if (TARGET==F2407)
688 ******************************************************
689 * FUNCTION DEF : _RstSystem
690 ******************************************************
691 007c _RstSystem:
692 007c 8aa0 POPD *+
693 007d 80a0 SAR AR0,*+
694 007e 8180 SAR AR1,*
695 007f b001 LARK AR0,1
696 0080 00e0 LAR AR0,*0+
697
698 .line 42
699 ;>>>> disable_ints(); /* Make sure the interrupts are disabled */
700 0081 7a80 CALL _disable_ints
0082 0000!
701 .line 43
702 ;>>>> IMR = 0x00; /* Mask all interrupts */
703 0083 b304 LARK AR3,4
704 0084 b900 LACK 0
705 0085 8b8b MAR * ,AR3
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 16
706 0086 9080 SACL *
707 .line 44
708 ;>>>> IFR = 0x00ff; /* Clear any pending interrupts, if any */
709 0087 b9ff LACK 255
710 0088 7802 ADRK 2
711 0089 908c SACL * ,AR4
712 .line 45
713 ;>>>> PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
714 008a bf0c LARK AR4,28688
008b 7010
715 008c bf80 LACK 65534
008d fffe
716 008e 6e80 AND *
717 008f 9080 SACL *
718 .line 46
719 ;>>>> PIRQR2 = PIRQR2 & 0x0fffe; /* Clear pending PDP flag */
720 0090 bf80 LACK 65534
0091 fffe
721 0092 7802 ADRK 2
722 0093 6e80 AND *
723 0094 908d SACL * ,AR5
724 .line 48
725 ;>>>> EVAIFRA = EVAIFRA | 0x0001; /* Clear PDPINTA flag */
726 0095 bf0d LARK AR5,29743
0096 742f
727 0097 b901 LACK 1
728 0098 6d80 OR *
729 0099 9080 SACL *
730 .line 49
731 ;>>>> EVBIFRA = EVBIFRA | 0x0001; /* Clear PDPINTB flag */
732 009a bf0d LARK AR5,29999
009b 752f
733 009c b901 LACK 1
734 009d 6d80 OR *
735 009e 9080 SACL *
736 .line 51
737 ;>>>> asm(" CLRC SXM "); /* Clear signextension mode */
738 009f be46 CLRC SXM
739 .line 52
740 ;>>>> asm(" CLRC OVM "); /* Reset overflow mode */
741 00a0 be42 CLRC OVM
742 .line 53
743 ;>>>> asm(" CLRC CNF "); /* Config block B0 to data memory */
744 00a1 be44 CLRC CNF
745 .line 54
746 ;>>>> asm(" SPM 0 "); /* Set product mode at 0 */
747 00a2 bf00 SPM 0
748 .line 56
749 ;>>>> WSGR=WAIT_STATES; /* Initialize Wait State Generator */
750 00a3 8b8b MAR * ,AR3
751 00a4 78ba ADRK 186
752 00a5 8b88 MAR * ,AR0
753 00a6 8380 SAR AR3,*
754 00a7 0c8b OUT * ,0ffffh,AR3
TMS320C24xx COFF Assembler Version 7.02 Fri Jul 07 11:06:57 2006
Copyright (c) 1987-2002 Texas Instruments Incorporated
../temp/bldc.asm PAGE 17
00a8 ffff
755 .line 57
756 ;>>>> SCSR1=0x0085; /* Init SCSR1 */
757 00a9 7c3b SBRK 59
758 00aa 8b8c MAR * ,AR4
759 00ab 7806 ADRK 6
760 00ac 8389 SAR AR3,* ,AR1
761 .line 58
762 ;>>>> wdog.disable(); /* Vccp/Wddis pin/bit must be high */
763 00ad bc00- LDPK _wdog
764 00ae 1054- LAC _wdog
765 00af be30 CALA
766 .line 59
767 ;>>>> wdog.reset(); /* reset watchdog counter */
768 00b0 bc00- LDPK _wdog+1
769 00b1 1055- LAC _wdog+1
770 00b2 be30 CALA
771 .line 61
772 ;>>>> EVAIMRB=0x0004; /* Enable the timer underflow interrupt */
773 00b3 bf0b LARK AR3,29741
00b4 742d
774 00b5 b904 LACK 4
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