📄 arm_isr.s
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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : arm_isr.s
;- Object : Example of IT handler calling a C function
;- Compilation flag : None
;-
;- 1.0 26/11/02 FB : Creation ARM ADS
;------------------------------------------------------------------------------
AREA itHandler, CODE, READONLY
;------------------------------------------------------------------------------
;- LISR vector handler for system peripherals
;--------------------------------------------
;- This macro save the context, call the LISR dispatch routine, and restore
;- the context
;------------------------------------------------------------------------------
INCLUDE AT91RM9200.inc
;--------------------------------
;- ARM Core Mode and Status Bits
;--------------------------------
ARM_MODE_USER EQU 0x10
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
ARM_MODE_ABORT EQU 0x17
ARM_MODE_UNDEF EQU 0x1B
ARM_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
T_BIT EQU 0x20
;------------------------------------------------------------------------------
;- IRQ Entry
;-----------
;[DDI0100E_ARM_ARM.pdf 2.6.6 Interrupt Request(IRQ)exception]
; The IRQ exception is generated externally by asserting the IRQ input on the
; processor. It has a lower priority than FIQ(see Table 2-4 on page A2-20),and
; is masked out when an FIQ sequence is entered.
; Interrupts are disabled when the I bit in the CPSR is set.If the I bit is clear,
; ARM checks for an IRQ at instruction boundaries.
; ----Note----
; The I bit can only be changed from a privileged Mode
; --------------------------------------------------------
; When an IRQ is detected,the following actions are performed:
; R14_irq = address of next instruction to be executed + 4
; SPSR_irq = CPSR
; CPSR[4:0] = 0b10010 /*Enter IRQ mode*/
; CPSR[[5] = 0 /*Execute in ARM state*/
; /*CPSR[6] is unchanged*/
; CPSR[7] = 1 /*Disable normal interrupts*/
; if high vectors configured then
; PC = 0xFFFF0018
; else
; PC = 0x00000018
;
; To return after serviceing the interrupt,use:
; SUBS PC,R14,#4
; this restores both the PC(from R14_irq) and CPSR(from SPSR_irq),and resumes
; execution of the interrupted code
;------------------------------------------------------------------------------
;[doc1768.pdf AT91RM9200 16.7.5 Protect Mode]
;The Protect Mode permits reading the Interrupt Vector Register without performing the associated
;automatic operations. This is necessary when working with a debug system. When a
;debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications
;and updates the opened windows, it might read the AIC User Interface and thus the IVR.
;This has undesirable consequences:
;? If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
;? If there is no enabled pending interrupt, the spurious vector is returned.
;In either case, an End of Interrupt command is necessary to acknowledge and to restore the
;context of the AIC. This operation is generally not performed by the debug system as the debug
;system would become strongly intrusive and cause the application to enter an undesired state.
;This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register)
;at 0x1 enables the Protect Mode.
;When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access
;is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary
;data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the
;Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is
;written.
;An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the
;AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to
;not stop the processor between the read and the write of AIC_IVR of the interrupt service routine
;to make sure the debugger does not modify the AIC context.
;To summarize, in normal operating mode, the read of AIC_IVR performs the following operations
;within the AIC:
;1. Calculates active interrupt (higher than current or spurious).
;2. 2. Determines and returns the vector of the active interrupt.
;3. Memorizes the interrupt.
;4. Pushes the current priority level onto the internal stack.
;5. Acknowledges the interrupt.
;However, while the Protect Mode is activated, only operations 1 to 3 are performed when
;AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written.
;Software that has been written and debugged using the Protect Mode runs correctly in Normal
;Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can
;be removed to optimize the code.
MACRO
IRQ_ENTRY $reg
;- Adjust and save LR_irq in IRQ stack
sub r14, r14, #4 ; now r14 = address of next instruction to be executed when exit(enter) IRQ
stmfd sp!, {r14}
;- Write in the IVR to support Protect Mode
;- No effect in Normal Mode
;- De-assert the NIRQ and clear the source in Protect Mode
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_IVR] ; if in protect mode,this dummy write update AIC,otherwise no effect
;- Save SPSR and r0 in IRQ stack
mrs r14, SPSR
stmfd sp!, {r0, r14}
;- Enable Interrupt and Switch in SYS Mode
mrs r0, CPSR
bic r0, r0, #I_BIT
orr r0, r0, #ARM_MODE_SYS
msr CPSR_c, r0
;- Save scratch/used registers and LR in User Stack
IF "$reg" = ""
stmfd sp!, { r1-r3, r12, r14}
ELSE
stmfd sp!, { r1-r3, $reg, r12, r14}
ENDIF
MEND
;------------------------------------------------------------------------------
;- IRQ Exit
; ---------
;------------------------------------------------------------------------------
MACRO
IRQ_EXIT $reg
;- Restore scratch/used registers and LR from User Stack
IF "$reg" = ""
ldmia sp!, { r1-r3, r12, r14}
ELSE
ldmia sp!, { r1-r3, $reg, r12, r14}
ENDIF
;- Disable Interrupt and switch back in IRQ mode
mrs r0, CPSR
bic r0, r0, #ARM_MODE_SYS
orr r0, r0, #I_BIT:OR:ARM_MODE_IRQ
msr CPSR_c, r0
;- Mark the End of Interrupt on the AIC
ldr r0, =AT91C_BASE_AIC
str r0, [r0, #AIC_EOICR]
;- Restore SPSR_irq and r0 from IRQ stack
ldmia sp!, {r0, r14}
msr SPSR_cxsf, r14
;- Restore adjusted LR_irq from IRQ stack directly in the PC
; [DDI0100E_ARM_ARM.pdf 4.1.19 LDM(3)]
; ^ For an LDM instruction that loads the PC, this indicates that the SPSR of the
; current mode is copied to the CPSR.
ldmia sp!, {pc}^
MEND
;------------------------------------------------------------------------------
; AT91F_ASM_SPI_Handler
; ---------------------
; Handler called by the AIC
;
; Save context
; Call C handler
; Restore context
;------------------------------------------------------------------------------
; EXPORT AT91F_ASM_SPI_Handler
; IMPORT AT91F_SPI_Handler
;
;AT91F_ASM_SPI_Handler
; IRQ_ENTRY
;
; ldr r1, =AT91F_SPI_Handler
; mov r14, pc
; bx r1
;
; IRQ_EXIT
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; AT91F_ASM_ST_DBGU_Handler
; ---------------------
; Handler called by the AIC
;
; Save context
; Call C handler
; Restore context
;------------------------------------------------------------------------------
EXPORT AT91F_ASM_ST_DBGU_Handler
IMPORT AT91F_ST_DBGU_Handler
AT91F_ASM_ST_DBGU_Handler
IRQ_ENTRY
ldr r1, =AT91F_ST_DBGU_Handler
mov r14, pc
bx r1
IRQ_EXIT
;------------------------------------------------------------------------------
END
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