init.c

at91rm9200的启动代码,开发环境ads1.2,这是本人学习过程中产生de

				AT91C_BASE_PMC->PMC_MCKR = 	MCKR_Register;
				while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );/* Wait until the master clock is established*/
			}

		}
	} else { /* just MDIV would be changed */
		if ( (t & AT91C_PMC_CSS) == AT91C_PMC_CSS_SLOW_CLK ) {
			AT91C_BASE_PMC->PMC_MCKR = 	(MCKR_Register & (AT91C_PMC_MDIV|AT91C_PMC_PRES))+AT91C_PMC_CSS_PLLA_CLK;
			while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );/* Wait until the master clock is established*/
		}
		else {
			AT91C_BASE_PMC->PMC_MCKR = 	(MCKR_Register & (AT91C_PMC_MDIV|AT91C_PMC_PRES))+AT91C_PMC_CSS_SLOW_CLK;
			while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );/* Wait until the master clock is established*/
		}
		AT91C_BASE_PMC->PMC_MCKR = 	MCKR_Register ;
		while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );/* Wait until the master clock is established*/
	}

	return TRUE;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_InitSDRAM
//* \brief This function performs very low level HW initialisation
//*----------------------------------------------------------------------------
void AT91F_InitSDRAM()
{
	int 	i;
	int 	*pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;

	//* Configure PIOC as peripheral (D16/D31)
	//4.3 Peripheral Multiplexing on PIO Lines
	AT91F_SDRC_CfgPIO();

	/**
	 * Setup MEMC to support CS1=SDRAM
	 * 1 :cs1 is assigned to the SDRAM Controller
	 * 0 :cs1 is assigned to the Static Memory Controller
	 *bit0=EBI_DBPUC  0 = D0-D15 Data Bus bits are internally pulled-up to the VDDIOM power supply.
	 *                1 = D0-D15 Data Bus bits are not internally pulled-up.
	 *bit1=EBI_EBSEN  0 = The External Bus Sharing feature is disabled.
	 *                1 = The External Bus Sharing feature is enabled.
	 */
	AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A;
	AT91C_BASE_EBI->EBI_CFGR = (AT91C_EBI_DBPUC & 0x00) | (AT91C_EBI_EBSEN & 0x00);

	//* Init SDRAM

	/**
	 * 1. A minimum pause of 200us is provided to precede any signal toggle
	 *  200us 延迟不知道是怎么实现的.是否是复位以后直到执行到此处的时间,这样的话
	 *  因为在时钟初始化以前是用32768Hz的时钟运行的,所以时间是足够的,但是不知道
	 *  管脚的复位电平是否符合SDRAM的初始化要求.
	 *      A0-A25 = 0 (DOC1768.PDF 4.3.5 TABLE4-7(P26))
	 *      D0-D31 = PULL-UP INPUT (DOC1768.PDF 4.3.5 TABLE4-7(P26))
	 *      SDCK   = MCK(MCK direct line to memory controller)  (Figure 17-1. Power Management Controller Block Diagram)
	 *      SDCS   = 1 (和NDCS1是同一管脚)
	 *      SDWE   = X   (DOC1768.PDF 4.3.5 TABLE4-7(P26))
	 *      RAS    = X   (DOC1768.PDF 4.3.5 TABLE4-7(P26))
	 *      CAS    = X   (DOC1768.PDF 4.3.5 TABLE4-7(P26))
	 *      BA0    = A16 (复用)
	 *      BA1    = A17 (复用)
	 *      SDA10  = A10 (复用)
	 */
//	AT91C_BASE_SDRC->SDRC_CR = AT91C_SDRC_NC_9 | AT91C_SDRC_NR_12 | AT91C_SDRC_NB_4_BANKS
//	                            | AT91C_SDRC_CAS_2
//								| 0x100 | 0x4000 | 0x8000
//								| 0x880000
//								| 0x21000000;

	/*for MT48LC8M16A2-75*/
	AT91C_BASE_SDRC->SDRC_CR =    AT91C_SDRC_NC_9           /*9  NC: Number of Column Bits*/
	                            | AT91C_SDRC_NR_12          /*12 NR: Number of Row Bits*/
	                            | AT91C_SDRC_NB_4_BANKS     /*4  NB: Number of Banks*/
	                            | AT91C_SDRC_CAS_2          /*2   MCK cycles CAS: CAS Latency*/
								| (0x2<<7)                  /*2   MCK cycles. TWR: Write Recovery Delay*/
								| (0x8<<11)                 /*8   MCK cycles. TRC: Row Cycle Delay*/
								| (0x2<<15)                 /*2   MCK cycles. TRP: Row Precharge Delay*/
								| (0x2<<19)                 /*2   MCK cycles. TRCD: Row to Column Delay*/
								| (0x3<<23)                 /*3   MCK cycles. TRAS: Active to Precharge Delay*/
								| (0x4<<27) ;               /*4.5 MCK cycles. TXSR: Exit Self Refresh to Active Delay*/


	//* 2. A Precharge All command is issued to the SDRAM
	AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;  /*this command issued by the SDRAM Controller when the SDRAM device is accessed.*/
	*pSDRAM = 0;

	//* 3. Eight Auto-refresh are provided
	AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
	for(i=0;i<8;i++)
		*pSDRAM = 0;

	//* 4. A mode register cycle is issued to program the SDRAM parameters
	/**
	 *The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed
	 *regardless of the cycle. The address offset with respect to the SDRAM device base address is used to
	 *program the Mode Register. For instance, when this mode is activated, an access to the "SDRAM_Base +
	 *offset" address generates a "Load Mode Register" command with the value "offset" written to the SDRAM
	 *device Mode Register.
	 */
	AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
	*(pSDRAM+0x80) = 0;     /*mode register = 0x20 because of mpu_a2=sdram_a0 see schmatic*/

	//* 5. Write refresh rate into SDRAMC refresh timer COUNT register
	AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT & 0x2E0);
	*pSDRAM = 0;

	//* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
	AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NORMAL_CMD;
	*pSDRAM = 0;
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_DBGU_Printk
//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
//*----------------------------------------------------------------------------
void AT91F_DBGU_Printk(
	char *buffer) // \arg pointer to a string ending by \0
{
	while(*buffer != '\0') {
		while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU)); /*poll mode*/
		AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
	}
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DataAbort
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_SpuriousHandler()
{
	AT91F_DBGU_Printk("-F- Spurious Interrupt detected\n\r");
	while (1);
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_DataAbort
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_DataAbort()
{
	AT91F_DBGU_Printk("-F- Data Abort detected\n\r");
	while (1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_FetchAbort
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_FetchAbort()
{
	AT91F_DBGU_Printk("-F- Prefetch Abort detected\n\r");
	while (1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_Undef
//* \brief This function reports an Abort
//*----------------------------------------------------------------------------
void AT91F_Undef()
{
	AT91F_DBGU_Printk("-F- Undef detected\n\r");
	while (1);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_UndefHandler
//* \brief This function reports that no handler have been set for current IT
//*----------------------------------------------------------------------------
void AT91F_UndefHandler()
{
	AT91F_DBGU_Printk("-F- Undef detected\n\r");
	while (1);
}


//*----------------------------------------------------------------------------
//* \fn    AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//*----------------------------------------------------------------------------
// *****************
// Exception Vectors
// *****************
// +------------------------------------------------------------+------------------------------------+--------------+------------+
// |复位        Reset                                           |  特权模式(Supervisor,sve)          |  0x00000000  | 0xffff0000 |
// |未定义指令  Undefined instructions                          |  未定义指令中止模式(Undefined,und) |  0x00000004  | 0xffff0004 |
// |软件中断    Software interrupt(SWI)                         |  特权模式(Supervisor,sve)          |  0x00000008  | 0xffff0008 |
// |指令预取中止Prefetch Abort(instruction fetch memory abort)  |  数据访问中止(Abort,abt)           |  0x0000000c  | 0xffff000c |
// |数据访问中止Data Abort(data access memory abort)            |  数据访问中止(Abort,abt)           |  0x00000010  | 0xffff0010 |
// |保留                                                        |                                    |  0x00000014  | 0xffff0014 |
// |外部中断请求IRQ(interrupt)                                  |  外部中断模式(IRQ,irq)             |  0x00000018  | 0xffff0018 |
// |快速中断请求FIQ(fast interrupt)                             |  快速中断模式（FIQ,fiq)            |  0x0000001c  | 0xffff001c |
// +------------------------------------------------------------+------------------------------------+--------------+------------+
void AT91F_LowLevelInit()
{
	volatile unsigned char 	status;
	int i;

	/* --- Step 2.
	 *--------------------------------
	 * Checking the Main Oscillator Frequency (Optional)
	 */
	status = AT91F_WaitForMainClockFrequency();


	/* --- Step 3. to 5.
	 *----------------------------------
     *PLLAR(step 3.),PLLBR(step 4.),MCKR(step 5.) define on the head in this file
     *INIT PCK(Processor clk)=179.712000MHz MCK(master clk)=59.904MHz
     */
	status = AT91F_InitClocks(PLLAR,PLLBR,MCKR);

	/* --- SDRAM Initialisation
	 *----------------------------------
	 */
	AT91F_InitSDRAM();


	/* --- Init Interrupt Controller
	 *----------------------------------
	 */
	/* disable all interrupts */
	for ( i = 0; i < 32; i++ )
		AT91F_AIC_DisableIt(AT91C_BASE_AIC, i);

	AT91F_AIC_Open(
		AT91C_BASE_AIC,          /* pointer to the AIC registers        */
		AT91C_AIC_BRANCH_OPCODE, /* Default IRQ vector exception        */
		AT91F_UndefHandler,      /* Default FIQ vector exception        */
		AT91F_UndefHandler,      /* Default Handler set in ISR          */
		AT91F_SpuriousHandler,   /* Default Spurious Handler            */
		0);                      /* Debug Control Register(Protect mode)*/

	/* Perform 8 End Of Interrupt Command to make the AIC will not Lock out nIRQ*/
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
	AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);

	AT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort);  /*指令预取中止Prefetch Abort(instruction fetch memory abort)*/
	AT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort);   /*数据访问中止Data Abort(data access memory abort)*/
	AT91F_AIC_SetExceptionVector((unsigned int *)0x4, AT91F_Undef);        /*未定义指令  Undefined instructions*/


	// Open PIO for DBGU
	AT91F_DBGU_CfgPIO();

	// Configure DBGU
	AT91F_US_Configure (
		(AT91PS_USART) AT91C_BASE_DBGU,     /*pointer to a USART controller */
		MCK,             					/*peripheral clock              */
		AT91C_US_ASYNC_MODE,        		/*mode Register to be programmed*/
		BAUDRATE ,              			/*baudrate to be programmed     */
		0);                   				/*timeguard to be programmed    */

	// Enable Transmitter
	AT91F_US_EnableTx((AT91PS_USART) AT91C_BASE_DBGU);
	// Enable Receiver
	AT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU);

	AT91F_DBGU_Printk("\n\rAT91F_LowLevelInit(): Debug channel initialized");
	AT91F_DBGU_Printk("\n\rthis message use 'AT91F_DBGU_Printk()' print out\n\r");
}