📄 lcdh.txt
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DEFCW( DMACTL2 , DMACTL2_)
#define DMACTL3_ (0x0506u) /* DMA Module Control 3 */
DEFCW( DMACTL3 , DMACTL3_)
#define DMACTL4_ (0x0508u) /* DMA Module Control 4 */
DEFCW( DMACTL4 , DMACTL4_)
#define DMAIV_ (0x050Eu) /* DMA Interrupt Vector Word */
DEFCW( DMAIV , DMAIV_)
#define DMA0CTL_ (0x0510u) /* DMA Channel 0 Control */
DEFCW( DMA0CTL , DMA0CTL_)
#define DMA0SA_ (0x0512u) /* DMA Channel 0 Source Address */
DEFA( DMA0SA , DMA0SA_)
#define DMA0DA_ (0x0516u) /* DMA Channel 0 Destination Address */
DEFA( DMA0DA , DMA0DA_)
#define DMA0SZ_ (0x051Au) /* DMA Channel 0 Transfer Size */
DEFW( DMA0SZ , DMA0SZ_)
#define DMA1CTL_ (0x0520u) /* DMA Channel 1 Control */
DEFCW( DMA1CTL , DMA1CTL_)
#define DMA1SA_ (0x0522u) /* DMA Channel 1 Source Address */
DEFA( DMA1SA , DMA1SA_)
#define DMA1DA_ (0x0526u) /* DMA Channel 1 Destination Address */
DEFA( DMA1DA , DMA1DA_)
#define DMA1SZ_ (0x052Au) /* DMA Channel 1 Transfer Size */
DEFW( DMA1SZ , DMA1SZ_)
#define DMA2CTL_ (0x0530u) /* DMA Channel 2 Control */
DEFCW( DMA2CTL , DMA2CTL_)
#define DMA2SA_ (0x0532u) /* DMA Channel 2 Source Address */
DEFA( DMA2SA , DMA2SA_)
#define DMA2DA_ (0x0536u) /* DMA Channel 2 Destination Address */
DEFA( DMA2DA , DMA2DA_)
#define DMA2SZ_ (0x053Au) /* DMA Channel 2 Transfer Size */
DEFW( DMA2SZ , DMA2SZ_)
/* DMACTL0 Control Bits */
#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */
#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */
#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */
#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */
#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */
#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */
#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */
#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */
#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */
/* DMACTL0 Control Bits */
#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */
#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */
#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */
#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */
/* DMACTL0 Control Bits */
#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */
#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */
#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */
#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */
#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */
/* DMACTL01 Control Bits */
#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */
#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */
#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */
#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */
#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */
/* DMACTL01 Control Bits */
#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */
#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */
#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */
#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */
#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */
/* DMACTL01 Control Bits */
/* DMACTL4 Control Bits */
#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */
#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */
#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
/* DMACTL4 Control Bits */
#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */
#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */
#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */
/* DMACTL4 Control Bits */
/* DMAxCTL Control Bits */
#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */
#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */
#define DMAIE (0x0004u) /* DMA interrupt enable */
#define DMAIFG (0x0008u) /* DMA interrupt flag */
#define DMAEN (0x0010u) /* DMA enable */
#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */
#define DMASRCBYTE (0x0040u) /* DMA source byte */
#define DMADSTBYTE (0x0080u) /* DMA destination byte */
#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */
#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */
#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */
#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */
#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */
#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */
#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */
/* DMAxCTL Control Bits */
#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */
#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */
#define DMAIE_L (0x0004u) /* DMA interrupt enable */
#define DMAIFG_L (0x0008u) /* DMA interrupt flag */
#define DMAEN_L (0x0010u) /* DMA enable */
#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */
#define DMASRCBYTE_L (0x0040u) /* DMA source byte */
#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */
/* DMAxCTL Control Bits */
#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */
#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */
#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */
#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */
#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */
#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */
#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */
#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */
/* DMAIV Definitions */
#define DMAIV_NONE (0x0000u) /* No Interrupt pending */
#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/
#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/
#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/
#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: Reserved */
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: Reserved */
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: Reserved */
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: Reserved */
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: Reserved */
#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12: Reserved */
#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13: Reserved */
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: Reserved */
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: Reserved */
#define DMA0TSEL_16 (16*0x0001u) /* DMA channel 0 transfer select 16: USCIA0 receive */
#define DMA0TSEL_17 (17*0x0001u) /* DMA channel 0 transfer select 17: USCIA0 transmit */
#define DMA0TSEL_18 (18*0x0001u) /* DMA channel 0 transfer select 18: USCIB0 receive */
#define DMA0TSEL_19 (19*0x0001u) /* DMA channel 0 transfer select 19: USCIB0 transmit */
#define DMA0TSEL_20 (20*0x0001u) /* DMA channel 0 transfer select 20: USCIA1 receive */
#define DMA0TSEL_21 (21*0x0001u) /* DMA channel 0 transfer select 21: USCIA1 transmit */
#define DMA0TSEL_22 (22*0x0001u) /* DMA channel 0 transfer select 22: USCIB1 receive */
#define DMA0TSEL_23 (23*0x0001u) /* DMA channel 0 transfer select 23: USCIB1 transmit */
#define DMA0TSEL_24 (24*0x0001u) /* DMA channel 0 transfer select 24: ADC12IFGx */
#define DMA0TSEL_25 (25*0x0001u) /* DMA channel 0 transfer select 25: Reserved */
#define DMA0TSEL_26 (26*0x0001u) /* DMA channel 0 transfer select 26: Reserved */
#define DMA0TSEL_27 (27*0x0001u) /* DMA channel 0 transfer select 27: Reserved */
#define DMA0TSEL_28 (28*0x0001u) /* DMA channel 0 transfer select 28: Reserved */
#define DMA0TSEL_29 (29*0x0001u) /* DMA channel 0 transfer select 29: Multiplier ready */
#define DMA0TSEL_30 (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
#define DMA0TSEL_31 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
#define DMA1TSEL_0 (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
#define DMA1TSEL_1 (1*0x0100u) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA1TSEL_2 (2*0x0100u) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
#define DMA1TSEL_3 (3*0x0100u) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA1TSEL_4 (4*0x0100u) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
#define DMA1TSEL_5 (5*0x0100u) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */
#define DMA1TSEL_6 (6*0x0100u) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */
#define DMA1TSEL_7 (7*0x0100u) /* DMA channel 1 transfer select 7: Reserved */
#define DMA1TSEL_8 (8*0x0100u) /* DMA channel 1 transfer select 8: Reserved */
#define DMA1TSEL_9 (9*0x0100u) /* DMA channel 1 transfer select 9: Reserved */
#define DMA1TSEL_10 (10*0x0100u) /* DMA channel 1 transfer select 10: Reserved */
#define DMA1TSEL_11 (11*0x0100u) /* DMA channel 1 transfer select 11: Reserved */
#define DMA1TSEL_12 (12*0x0100u) /* DMA channel 1 transfer select 12: Reserved */
#define DMA1TSEL_13 (13*0x0100u) /* DMA channel 1 transfer select 13: Reserved */
#define DMA1TSEL_14 (14*0x0100u) /* DMA channel 1 transfer select 14: Reserved */
#define DMA1TSEL_15 (15*0x0100u) /* DMA channel 1 transfer select 15: Reserved */
#define DMA1TSEL_16 (16*0x0100u) /* DMA channel 1 transfer select 16: USCIA0 receive */
#define DMA1TSEL_17 (17*0x0100u) /* DMA channel 1 transfer select 17: USCIA0 transmit */
#define DMA1TSEL_18 (18*0x0100u) /* DMA channel 1 transfer select 18: USCIB0 receive */
#define DMA1TSEL_19 (19*0x0100u) /* DMA channel 1 transfer select 19: USCIB0 transmit */
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