📄 lcdh.txt
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#define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */
#define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */
#define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */
#define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */
#define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */
#define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */
#define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */
#define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */
#define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */
#define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */
#define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */
#define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */
#define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */
#define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */
#define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */
#define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */
#define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */
#define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */
#define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */
#define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */
#define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */
#define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */
#define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */
#define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */
#define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */
#define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */
#define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */
/* ADC12CTL2 Control Bits */
#define ADC12REFBURST (0x0001u) /* ADC12+ Reference Burst */
#define ADC12REFOUT (0x0002u) /* ADC12+ Reference Out */
#define ADC12SR (0x0004u) /* ADC12+ Sampling Rate */
#define ADC12DF (0x0008u) /* ADC12+ Data Format */
#define ADC12RES0 (0x0010u) /* ADC12+ Resolution Bit: 0 */
#define ADC12RES1 (0x0020u) /* ADC12+ Resolution Bit: 1 */
#define ADC12TCOFF (0x0080u) /* ADC12+ Temperature Sensor Off */
#define ADC12PDIV (0x0100u) /* ADC12+ predivider 0:/1 1:/4 */
/* ADC12CTL2 Control Bits */
#define ADC12REFBURST_L (0x0001u) /* ADC12+ Reference Burst */
#define ADC12REFOUT_L (0x0002u) /* ADC12+ Reference Out */
#define ADC12SR_L (0x0004u) /* ADC12+ Sampling Rate */
#define ADC12DF_L (0x0008u) /* ADC12+ Data Format */
#define ADC12RES0_L (0x0010u) /* ADC12+ Resolution Bit: 0 */
#define ADC12RES1_L (0x0020u) /* ADC12+ Resolution Bit: 1 */
#define ADC12TCOFF_L (0x0080u) /* ADC12+ Temperature Sensor Off */
/* ADC12CTL2 Control Bits */
#define ADC12PDIV_H (0x0001u) /* ADC12+ predivider 0:/1 1:/4 */
#define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */
#define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */
#define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */
#define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */
/* ADC12MCTLx Control Bits */
#define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */
#define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */
#define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */
#define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */
#define ADC12SREF0 (0x0010u) /* ADC12 Select Reference Bit 0 */
#define ADC12SREF1 (0x0020u) /* ADC12 Select Reference Bit 1 */
#define ADC12SREF2 (0x0040u) /* ADC12 Select Reference Bit 2 */
#define ADC12EOS (0x0080u) /* ADC12 End of Sequence */
#define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */
#define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */
#define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */
#define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */
#define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */
#define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */
#define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */
#define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */
#define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */
#define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */
#define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */
#define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */
#define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */
#define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */
#define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */
#define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */
#define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */
#define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */
#define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */
#define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */
#define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */
#define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */
#define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */
#define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */
#define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */
#define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */
#define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */
#define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */
#define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */
#define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */
#define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */
#define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */
#define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */
#define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */
#define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */
#define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */
#define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */
#define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */
#define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */
#define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */
#define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */
#define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */
#define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */
#define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */
#define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */
#define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */
#define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */
#define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */
#define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */
#define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */
#define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */
#define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */
#define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */
#define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */
#define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */
#define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */
#define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */
#define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */
#define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */
#define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */
#define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */
#define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */
#define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */
#define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */
#define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */
#define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */
#define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */
#define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */
#define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */
#define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */
#define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */
#define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */
#define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */
#define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */
#define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */
#define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */
#define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */
#define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */
#define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */
#define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */
#define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */
#define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */
#define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */
#define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */
#define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */
#define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */
#define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */
#define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */
/* ADC12IV Definitions */
#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */
#define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */
#define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */
#define ADC12IV_ADC12IFG0 (0x0006u) /* ADC12IFG0 */
#define ADC12IV_ADC12IFG1 (0x0008u) /* ADC12IFG1 */
#define ADC12IV_ADC12IFG2 (0x000Au) /* ADC12IFG2 */
#define ADC12IV_ADC12IFG3 (0x000Cu) /* ADC12IFG3 */
#define ADC12IV_ADC12IFG4 (0x000Eu) /* ADC12IFG4 */
#define ADC12IV_ADC12IFG5 (0x0010u) /* ADC12IFG5 */
#define ADC12IV_ADC12IFG6 (0x0012u) /* ADC12IFG6 */
#define ADC12IV_ADC12IFG7 (0x0014u) /* ADC12IFG7 */
#define ADC12IV_ADC12IFG8 (0x0016u) /* ADC12IFG8 */
#define ADC12IV_ADC12IFG9 (0x0018u) /* ADC12IFG9 */
#define ADC12IV_ADC12IFG10 (0x001Au) /* ADC12IFG10 */
#define ADC12IV_ADC12IFG11 (0x001Cu) /* ADC12IFG11 */
#define ADC12IV_ADC12IFG12 (0x001Eu) /* ADC12IFG12 */
#define ADC12IV_ADC12IFG13 (0x0020u) /* ADC12IFG13 */
#define ADC12IV_ADC12IFG14 (0x0022u) /* ADC12IFG14 */
#define ADC12IV_ADC12IFG15 (0x0024u) /* ADC12IFG15 */
/*************************************************************
* CRC Module
*************************************************************/
#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */
#define CRCDI_ (0x0150u) /* CRC Data In Register */
DEFCW( CRCDI , CRCDI_)
#define CRCDIRB_ (0x0152u) /* CRC data in reverse byte Register */
DEFCW( CRCDIRB , CRCDIRB_)
#define CRCINIRES_ (0x0154u) /* CRC Initialisation Register and Result Register */
DEFCW( CRCINIRES , CRCINIRES_)
#define CRCRESR_ (0x0156u) /* CRC reverse result Register */
DEFCW( CRCRESR , CRCRESR_)
/************************************************************
* DMA_X
************************************************************/
#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
#define DMACTL0_ (0x0500u) /* DMA Module Control 0 */
DEFCW( DMACTL0 , DMACTL0_)
#define DMACTL1_ (0x0502u) /* DMA Module Control 1 */
DEFCW( DMACTL1 , DMACTL1_)
#define DMACTL2_ (0x0504u) /* DMA Module Control 2 */
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