📄 s1d13806.h
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/*----------------------------------------------- -----*/
/* S1D13806 SDRAM Refresh Counter Bits Definition */
/*------------------------------------------- ---------*/
#define S1D_RR_0 0x00 /* Configuration 0 programmed */
#define S1D_RR_1 0x01 /* Configuration 1 programmed */
#define S1D_RR_2 0x02 /* Configuration 2 programmed */
#define S1D_RR_3 0x03 /* Configuration 3 programmed */
/*-----------------------------------------------------*/
/* S1D13806 SDRAM Timing Control Bits Definition */
/*-----------------------------------------------------*/
#define S1D_TC_0_0 0x00 /* Configuration 0 programmed register 0 */
#define S1D_TC_0_1 0x01 /* Configuration 0 programmed register 1 */
#define S1D_TC_1_0 0x00 /* Configuration 1 programmed register 0 */
#define S1D_TC_1_1 0x12 /* Configuration 1 programmed register 1 */
#define S1D_TC_2_0 0x11 /* Configuration 2 programmed register 0 */
#define S1D_TC_2_1 0x13 /* Configuration 2 programmed register 1 */
/*-------------------------------------------*/
/* S1D13806 Panel Type Bits Definition */
/*-------------------------------------------*/
#define S1D_EL_PAN_EN 0x80 /* EL Panel Mode Enabled */
#define S1D_TFT_DF 0x40 /* Switch TFT Standard (0) or 2X (1) Data Format */
#define S1D_PAN_DW_0 0x00 /* Panel Data Width Configuration 0 programmed */
#define S1D_PAN_DW_1 0x10 /* Panel Data Width Configuration 1 programmed */
#define S1D_PAN_DW_2 0x20 /* Panel Data Width Configuration 2 programmed */
#define S1D_PAN_DF 0x08 /* Switch Panel Data Format 1 (0) or 2 (1) */
#define S1D_PAN_CM 0x04 /* Switch Panel monochrome (0) or color (1) */
#define S1D_PAN_DS 0x02 /* Switch Panel single (0) or dual (1) */
#define S1D_PAN_TL 0x01 /* Switch Panel LCD (0) or TFT (1) */
/*---------------------------------------------------*/
/* S1D13806 FPLINE & FPFRAME Polarity Definition */
/*---------------------------------------------------*/
#define S1D_FPPOL 0x80 /* Switch TFT active low and LCD active high (0) or
TFT active high and LCD active low (1) */
/*--------------------------------------------------------------*/
/* S1D13806 Vertical Non-Display Period Status Definition */
/*--------------------------------------------------------------*/
#define S1D_VNDPS_MASK 0x80 /* Status Mask */
#define S1D_VNDP 0x80 /* LCD Panel Vertical Non-Display Output */
#define S1D_VDP 0x00 /* LCD Panel Output is in a Vertical Display Output */
/*----------------------------------------------------------*/
/* S1D13806 LCD & CRT/TV Display Mode Bits Definition */
/*----------------------------------------------------------*/
#define S1D_LCDDIS 0x80 /* Switch LCD Display Enabled (0) or Disabled (1) */
#define S1D_LCDSWIVEL1 0x10 /* Switch LCD SwivelView Disabled (0) or Enabled (1) */
#define S1D_4BPP 0x02 /* LCD & CRT/TV 4 Bit-per-pixel selection */
#define S1D_8BPP 0x03 /* LCD & CRT/TV 8 Bit-per-pixel selection */
#define S1D_16BPP 0x05 /* LCD & CRT/TV 16 Bit-per-pixel selection */
/*-----------------------------------------------------------*/
/* S1D13806 LCD Miscellaneous Register Bits Definition */
/*-----------------------------------------------------------*/
#define S1D_LCDDEN 0x02 /* Switch Dithering Enabled (0) or Disabled (1) */
#define S1D_DPANEN 0x01 /* Switch Dual Panel Buffer Enabled (0) or Disabled (1) */
/*------------------------------------------------*/
/* S1D13806 HRTC & VRTC Polarity Definition */
/*------------------------------------------------*/
#define S1D_RTCPOL 0x80 /* Switch HRTC (or VRTC) pulse active low (0) or
HRTC (or VRTC) pulse active high (1) */
/*-----------------------------------------------------------*/
/* S1D13806 TV Output Control Register Bits Definition */
/*-----------------------------------------------------------*/
#define S1D_CHROFILEN 0x20 /* Switch TV Chrominance Filter Disabled (0) or Enabled (1) */
#define S1D_LUFILEN 0x10 /* Switch TV Luminance Filter Disabled (0) or Enabled (1) */
#define S1D_DOLSEL 0x08 /* Select IREF reduced when set (1) */
#define S1D_SVCSEL 0x02 /* Select Composite Output when reset (0), S-Video when set (1) */
#define S1D_PALNTSEL 0x01 /* Select NTSC Format Output when reset (0), PAL Format Output when set (1) */
/*----------------------------------------------------*/
/* S1D13806 CRT/TV Display Mode Bits Definition */
/*----------------------------------------------------*/
#define S1D_CRTDIS 0x80 /* Switch CRT/TV Display Enabled (0) or Disabled (1) */
/*-------------------------------------------------------------------------*/
/* S1D13806 LCD & CRT/TV Ink/Cursor Control Register Bits Definition */
/*-------------------------------------------------------------------------*/
#define S1D_NOINKCUR 0x00 /* LCD & CRT/TV Ink/Cursor circuitry disabled */
#define S1D_CUREN 0x01 /* LCD & CRT/TV Cursor Enabled */
#define S1D_INKEN 0x02 /* LCD & CRT/TV Ink Enabled */
/*---------------------------------------------------------*/
/* S1D13806 BitBLT Control Registers Bits Definition */
/*---------------------------------------------------------*/
#define S1D_BBLTAS 0x80 /* 2D Operation initiated & busy */
#define S1D_BBLTFNES 0x40 /* BitBLT FIFO Not Empty Status */
#define S1D_BBLTHFS 0x20 /* BitBLT Half Full Status */
#define S1D_BBLTFS 0x10 /* BitBLT FIFO Full Status */
#define S1D_BBLTDLS 0x02 /* Destination BitBLT stored as a contiguous linear block of memory */
#define S1D_BBLTSLS 0x01 /* Source BitBLT stored as a contiguous linear block of memory */
#define S1D_BBLTCFS 0x01 /* Switch between 8 Bit-per-pixel 2D Operation Color Format (0) or
16 Bit-per-pixel (1) */
/*------------------------------------------------------------*/
/* S1D13806 Look-Up Table Mode Register Bits Definition */
/*------------------------------------------------------------*/
#define S1D_LCDLUTRW_CRTLUTW 0x00 /* LCD LUT Read & Write, CRT/TV LUT Write */
#define S1D_LCDLUTRW 0x01 /* LCD LUT Read & Write */
#define S1D_CRTLUTRW 0x02 /* CRT/TV LUT Read & Write */
/*---------------------------------------------------------*/
/* S1D13806 Power Save Configuration Bits Definition */
/*---------------------------------------------------------*/
#define S1D_PSMD 0x10 /* Switch Power Save Mode Disabled (0) or Enabled (1) */
#define S1D_PSME 0x11 /* Switch Power Save Mode Disabled (0) or Enabled (1) */
/*--------------------------------------------------*/
/* S1D13806 Power Save Status Bits Definition */
/*--------------------------------------------------*/
#define S1D_LCDPSS 0x02 /* Indicates LCD Panel Powered (0) or not (1) */
#define S1D_MCPSS 0x01 /* Indicates Memory Controller Powered (0) or not (1) */
/*-------------------------------------------------------------*/
/* S1D13806 Common Display Mode Register Bits Definition */
/*-------------------------------------------------------------*/
#define S1D_LCDSWIVEL0 0x40 /* Switch LCD SwivelView Disabled (0) or Enabled (1) */
#define S1D_NDM 0x00 /* No Display Mode */
#define S1D_LCDOM 0x01 /* LCD Only Display Mode */
#define S1D_CRTOM 0x02 /* CRT Only Display Mode */
#define S1D_EISD0M 0x03 /* EISD (CRT & LCD) Display Mode */
#define S1D_TVFFOFFM 0x04 /* TV with flicker filter off Display Mode */
#define S1D_EISD1M 0x05 /* EISD (TV with flicker filter off & LCD) Display Mode */
#define S1D_TVFFONM 0x06 /* TV with flicker filter on Display Mode */
#define S1D_EISD2M 0x07 /* EISD (TV with flicker filter on & LCD) Display Mode */
//////////////////////////////////////////////////////////////////////////////
// Standard Descriptor Structure Definition
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_DisplayDefDesc
{
short hdw ; /* Horizontal Display Width */
short vdw ; /* Vertical Display Width */
} AT91S_S1D13806_DisplayDefDesc, *AT91PS_S1D13806_DisplayDefDesc;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_CharDefDesc
{
int hnbp ; /* Horizontal Number of Pixels per Character */
int vnbp ; /* Vertical Number of Pixels per Character */
} AT91S_S1D13806_CharDefDesc, *AT91PS_S1D13806_CharDefDesc;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_DataDesc
{
int Present_lcd_start_address ; /* Current LCD Start Address */
int Present_crt_start_address ; /* Current CRT Start Address */
int Present_nb_char_on_line ; /* Current Line Number of Characters */
char *Present_display_mem_ptr ; /* Current Display Memory Pointer */
} AT91S_S1D13806_DataDesc, *AT91PS_S1D13806_DataDesc;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_RegDesc
{
short ioconf ; /* GPIO Initialization */
short iocr ; /* GPIO Initialization */
char mclk ; /* Clock Initialization */
char lcdclk ; /* Clock Initialization */
char crtpclk ; /* Clock Initialization */
char mpclk ; /* Clock Initialization */
char nws ; /* CPU Wait States */
char refc ; /* SDRAM Refres Counter */
short sdram ; /* SDRAM Timing Control */
char ptype ; /* Panel Configuration */
char mod ; /* Mode Rate */
char lcdhndp ; /* LCD Horizontal Non-Display Period */
char tftfpsp ; /* FPLINE Start Position */
char tftfppw ; /* FPLINE Pulse Width */
char lcdvndp ; /* LCD Vertical Non-Display Period */
char lcdfpsp ; /* FPFRAME Start Position */
char lcdfppw ; /* FPFRAME Pulse Width */
char lcddm ; /* LCD Display mode */
char lcdm ; /* LCD Miscellaneous */
short lcdmao ; /* LCD Memory Address Offset */
char crthndp ; /* CRT/TV Horizontal Non-Display Period */
char crthsp ; /* HRTC Start Position */
char crthpw ; /* HRTC Pulse Width */
char crtvndp ; /* CRT/TV Vertical Non-Display Period */
char crtvsp ; /* VRTC Start Position */
char crtvpw ; /* VRTC Pulse Width */
char tvoc ; /* TV Output */
char crtdm ; /* CRT Display Mode */
short crtmao ; /* CRT Memory Address Offset */
char lcdicc ; /* LCD Ink/Cursor Control */
char lcdicba ; /* LCD Ink/Cursor Start Address */
char lcdicb0 ; /* LCD Ink/Cursor Blue Color 0 */
char lcdicg0 ; /* LCD Ink/Cursor Green Color 0 */
char lcdicr0 ; /* LCD Ink/Cursor Red Color 0 */
char lcdicb1 ; /* LCD Ink/Cursor Blue Color 1 */
char lcdicg1 ; /* LCD Ink/Cursor Green Color 1 */
char lcdicr1 ; /* LCD Ink/Cursor Red Color 1 */
char crticc ; /* CRT/TV Ink/Cursor Control */
char crticba ; /* CRT/TV Ink/Cursor Start Address */
char crticb0 ; /* CRT/TV Ink/Cursor Blue Color 0 */
char crticg0 ; /* CRT/TV Ink/Cursor Green Color 0 */
char crticr0 ; /* CRT/TV Ink/Cursor Red Color 0 */
char crticb1 ; /* CRT/TV Ink/Cursor Blue Color 1 */
char crticg1 ; /* CRT/TV Ink/Cursor Green Color 1 */
char crticr1 ; /* CRT/TV Ink/Cursor Red Color 1 */
char lutm ; /* Look-Up Table Mode */
char psc ; /* Power Save Configuration */
char dm ; /* Display Mode */
} AT91S_S1D13806_RegDesc, *AT91PS_S1D13806_RegDesc;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_DisplayDesc
{
int s1d13806_base_add ; /* Device Base Address in EBI Space */
int s1d13806_disp_mem_base_add ; /* Display Memory Base Address in EBI Space */
AT91PS_S1D13806_RegDesc RegDesc ; /* Registers Description */
AT91PS_S1D13806_DisplayDefDesc DisplayDefDesc ; /* Display Definition Description */
AT91PS_S1D13806_CharDefDesc CharDefDesc ; /* Character Definition Description */
AT91PS_S1D13806_DataDesc DataDesc ; /* Data Descriptor */
} AT91S_S1D13806_DisplayDesc, *AT91PS_S1D13806_DisplayDesc;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_BitmapDesc
{
short type ; /* BM - bitmap type indicator */
int FileSize ;
short Reserved1 ;
short Reserved2 ;
int ImageOffset ; /* Image Data Offset - after Bitmap Descriptor */
int HeaderSize ; /* Bitmap Descriptor Size */
int width ; /* Horizontal Display Width */
int height ; /* Vertical Display Width */
short planes ; /* 1 */
short BitsPerPixel ; /* Bit-per-Pixel Representation */
int CompressionType ;
int ImageSize ; /* Image Data Size */
int xPerMetre ;
int yPerMetre ;
int ColoursUsed ;
int ImportantColours ;
} AT91S_S1D13806_BitmapDesc, *AT91PS_S1D13806_BitmapDesc;
//////////////////////////////////////////////////////////////////////////////
/*-----------------------------------*/
/* Bitmap File Constants Definitions */
/*-----------------------------------*/
#define BMP_FILE_TYPE 0x4D42
#define BMP_16BPP 16
#define BMP_24BPP 24
#define BMP_HEADER_SIZE ( sizeof ( AT91S_S1D13806_BitmapDesc ) )
/* Time constants definition */
#define TIMEOUT_OF_200us 2 // (2*100)us
/* Function Prototyping s1d13806.c */
extern void AT91F_S1D13806_Init ( AT91PS_S1D13806_Desc s1d13806_base, int s1d13806_disp_mem_base, unsigned int conf, unsigned int disp_def, unsigned int char_def, unsigned int mck_khz ) ;
extern void AT91F_S1D13806_16bpp_print_string ( AT91PS_S1D13806_Desc s1d13806_base, char *buff ) ;
#endif /* s1d13806_h */
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