📄 s1d13806.h
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//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : s1d13806.h
//* Object : Video Graphic Display Controller Prototyping File.
//*
//* 1.0 09/05/02 ED : Creation
//* 1.2 13/01/03 FB : Update on lib V3
//*----------------------------------------------------------------------------
#ifndef s1d13806_h
#define s1d13806_h
#define H_MAX_RES 800
#define V_MAX_RES 600
//////////////////////////////////////////////////////////////////////////////
// S1D13806 User Interface Structure Definition
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_OnChipReg
{
char OCR_REV ; /* Revision Code Register */
char OCR_MISC ; /* Miscellaneous Register */
char Reserved0[2] ; /* Reserved */
short OCR_IOCONF ; /* GPIO Configuration Register */
char Reserved1[2] ; /* Reserved */
short OCR_IOCR ; /* GPIO Control Register */
char Reserved2[2] ; /* Reserved */
char OCR_SR ; /* Status Register */
char Reserved3[3] ; /* Reserved */
char OCR_MCLK ; /* Memory Clock Configuration Register */
char Reserved4[3] ; /* Reserved */
char OCR_LCDCLK ; /* LCD Pixel Clock Configuration Register */
char Reserved5[3] ; /* Reserved */
char OCR_CRTPCLK ; /* CRT/TV Pixel Clock Configuration Register */
char Reserved6[3] ; /* Reserved */
char OCR_MPCLK ; /* MediaPlug Clock Configuration Register */
char Reserved7 ; /* Reserved */
char OCR_NWS ; /* CPU to Memory Wait States Configuration Register */
char Reserved8 ; /* Reserved */
char OCR_MEM ; /* Memory Configuration Register */
char OCR_REFC ; /* SDRAM Refresh Counter Register */
char Reserved9[8] ; /* Reserved */
short OCR_SDRAM ; /* SDRAM Configuration Register */
char Reserved10[4] ; /* Reserved */
char OCR_PTYPE ; /* Panel Type Configuration Register */
char OCR_MOD ; /* MOD Rate Configuration Register */
char OCR_LCDHDW ; /* LCD Horizontal Display Width Configuration Register */
char Reserved11 ; /* Reserved */
char OCR_LCDHNDP ; /* LCD Horizontal Non-Display Period Configuration Register */
char OCR_TFTFPSP ; /* TFT FPLINE Start Position Configuration Register */
char OCR_TFTFPPW ; /* TFT FPLINE Pulse Width Configuration Register */
char Reserved12 ; /* Reserved */
short OCR_LCDVDH ; /* LCD Vertical Display Height Configuration Register */
char OCR_LCDVNDP ; /* LCD Vertical Non-Display Period Configuration Register */
char OCR_LCDFPSP ; /* LCD FPFRAME Start Position Configuration Register */
char OCR_LCDFPPW ; /* LCD FPFRAME Pulse Width Configuration Register */
char Reserved13 ; /* Reserved */
char OCR_LCDLC ; /* LCD Line Count Configuration Register */
char Reserved14 ; /* Reserved */
char OCR_LCDDM ; /* LCD Display Mode Configuration Register */
char OCR_LCDM ; /* LCD Miscellaneous Configuration Register */
char OCR_LCDDBA_0 ; /* LCD Display Start Address Configuration Register 0 */
char OCR_LCDDBA_1 ; /* LCD Display Start Address Configuration Register 1 */
char OCR_LCDDBA_2 ; /* LCD Display Start Address Configuration Register 2 */
char Reserved15 ; /* Reserved */
short OCR_LCDMAO ; /* LCD Memory Address Offset Configuration Register */
char OCR_LCDPP ; /* LCD Pixel Planning Configuration Register */
char Reserved16 ; /* Reserved */
char OCR_LCDDFHTC ; /* LCD Display FIFO High Threshold Control Register */
char OCR_LCDDFLTC ; /* LCD Display FIFO Low Threshold Control Register */
char Reserved17[4] ; /* Reserved */
char OCR_CRTHDW ; /* CRT/TV Horizontal Display Width Configuration Register */
char Reserved18 ; /* Reserved */
char OCR_CRTHNDP ; /* CRT/TV Horizontal Non-Display Period Configuration Register */
char OCR_CRTHSP ; /* CRT/TV HRTC Start Position Configuration Register */
char OCR_CRTHPW ; /* CRT/TV HRTC Pulse Width Configuration Register */
char Reserved19 ; /* Reserved */
short OCR_CRTVDH ; /* CRT/TV Vertical Display Height Configuration Register */
char OCR_CRTVNDP ; /* CRT/TV Vertical Non-Display Period Configuration Register */
char OCR_CRTVSP ; /* CRT/TV VRTC Start Position Configuration Register */
char OCR_CRTVPW ; /* CRT/TV VRTC Pulse Width Configuration Register */
char OCR_TVOC ; /* TV Output Control Register */
char Reserved20[2] ; /* Reserved */
char OCR_CRTLC ; /* CRT/TV Line Count Configuration Register */
char Reserved21 ; /* Reserved */
char OCR_CRTDM ; /* CRT/TV Display Mode Configuration Register */
char Reserved22 ; /* Reserved */
char OCR_CRTDBA_0 ; /* CRT/TV Display Start Address Configuration Register 0 */
char OCR_CRTDBA_1 ; /* CRT/TV Display Start Address Configuration Register 1 */
char OCR_CRTDBA_2 ; /* CRT/TV Display Start Address Configuration Register 2 */
char Reserved23 ; /* Reserved */
short OCR_CRTMAO ; /* CRT/TV Memory Address Offset Configuration Register */
char OCR_CRTPP ; /* CRT/TV Pixel Planning Configuration Register */
char Reserved24 ; /* Reserved */
char OCR_CRTDFHTC ; /* CRT/TV Display FIFO High Threshold Control Register */
char OCR_CRTDFLTC ; /* CRT/TV Display FIFO Low Threshold Control Register */
char Reserved25[4] ; /* Reserved */
char OCR_LCDICC ; /* LCD Ink/Cursor Control Register */
char OCR_LCDICBA ; /* LCD Ink/Cursor Start Address Register */
short OCR_LCDCXP ; /* LCD Cursor X Position Register */
short OCR_LCDCYP ; /* LCD Cursor Y Position Register */
char OCR_LCDICB_0 ; /* LCD Ink/Cursor Blue Color Configuration Register 0 */
char OCR_LCDICG_0 ; /* LCD Ink/Cursor Green Color Configuration Register 0 */
char OCR_LCDICR_0 ; /* LCD Ink/Cursor Red Color Configuration Register 0 */
char Reserved26 ; /* Reserved */
char OCR_LCDICB_1 ; /* LCD Ink/Cursor Blue Color Configuration Register 1 */
char OCR_LCDICG_1 ; /* LCD Ink/Cursor Green Color Configuration Register 1 */
char OCR_LCDICR_1 ; /* LCD Ink/Cursor Red Color Configuration Register 1 */
char Reserved27 ; /* Reserved */
char OCR_LCDICFT ; /* LCD Ink/Cursor FIFO Threshold Configuration Register */
char Reserved28 ; /* Reserved */
char OCR_CRTICC ; /* CRT/TV Ink/Cursor Control Register */
char OCR_CRTICBA ; /* CRT/TV Ink/Cursor Start Address Register */
short OCR_CRTCXP ; /* CRT/TV Cursor X Position Register */
short OCR_CRTCYP ; /* CRT/TV Cursor Y Position Register */
char OCR_CRTICB_0 ; /* CRT/TV Ink/Cursor Blue Color Configuration Register 0 */
char OCR_CRTICG_0 ; /* CRT/TV Ink/Cursor Green Color Configuration Register 0 */
char OCR_CRTICR_0 ; /* CRT/TV Ink/Cursor Red Color Configuration Register 0 */
char Reserved29 ; /* Reserved */
char OCR_CRTICB_1 ; /* CRT/TV Ink/Cursor Blue Color Configuration Register 1 */
char OCR_CRTICG_1 ; /* CRT/TV Ink/Cursor Green Color Configuration Register 1 */
char OCR_CRTICR_1 ; /* CRT/TV Ink/Cursor Red Color Configuration Register 1 */
char Reserved30 ; /* Reserved */
char OCR_CRTICFT ; /* CRT/TV Ink/Cursor FIFO Threshold Configuration Register */
char Reserved31[113] ; /* Reserved */
short OCR_BBLTC ; /* BitBLT Control Register */
char OCR_BBLTRCCE ; /* BitBLT ROP Code/Color Expansion Register */
char OCR_BBLTO ; /* BitBLT Operation Register */
char OCR_BBLTSSA_0 ; /* BitBLT Source Start Address Register 0 */
char OCR_BBLTSSA_1 ; /* BitBLT Source Start Address Register 1 */
char OCR_BBLTSSA_2 ; /* BitBLT Source Start Address Register 2 */
char Reserved32 ; /* Reserved */
char OCR_BBLTDSA_0 ; /* BitBLT Destination Start Address Register 0 */
char OCR_BBLTDSA_1 ; /* BitBLT Destination Start Address Register 1 */
char OCR_BBLTDSA_2 ; /* BitBLT Destination Start Address Register 2 */
char Reserved33 ; /* Reserved */
short OCR_BBLTMAO ; /* BitBLT Memory Address Offset Register */
char Reserved34[2] ; /* Reserved */
short OCR_BBLTW ; /* BitBLT Width Register */
short OCR_BBLTH ; /* BitBLT Height Register */
short OCR_BBLTBC ; /* BitBLT Background Color Register */
char Reserved35[2] ; /* Reserved */
short OCR_BBLTFC ; /* BitBLT Foreground Color Register */
char Reserved36[198] ; /* Reserved */
char OCR_LUTM ; /* Look-Up Table Mode Register */
char Reserved37 ; /* Reserved */
char OCR_LUTBA ; /* Look-Up Table Base Address Register */
char Reserved38 ; /* Reserved */
char OCR_LUTD ; /* Look-Up Table Data Register */
char Reserved39[11] ; /* Reserved */
char OCR_PSC ; /* Power Save Configuration Register */
char OCR_PSS ; /* Power Save Status Register */
char Reserved40[2] ; /* Reserved */
char OCR_WDT ; /* CPU to Memory Access Watchdog Timer Configuration Register */
char Reserved41[7] ; /* Reserved */
char OCR_DM ; /* Display Mode Configuration Register */
char Reserved42[3] ; /* Reserved */
} AT91S_S1D13806_OnChipReg, *AT91PS_S1D13806_OnChipReg;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_MediaPlug
{
short MP_LCMD ; /* MediaPlug LCMD Configuration Register */
short MP_RLCMD ; /* MediaPlug Reserved LCMD Configuration Register */
short MP_CMD ; /* MediaPlug Command Configuration Register */
short MP_RCMD ; /* MediaPlug Reserved Command Configuration Register */
short MP_DBA ; /* MediaPlug Data Base Address */
} AT91S_S1D13806_MediaPlug, *AT91PS_S1D13806_MediaPlug;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_BitBLTReg
{
short BBR_DBA ; /* BitBLT Data Base Address */
}AT91S_S1D13806_BitBLTReg, *AT91PS_S1D13806_BitBLTReg;
//////////////////////////////////////////////////////////////////////////////
typedef struct _AT91S_S1D13806_Desc
{
AT91S_S1D13806_OnChipReg S1D13806_OnChipReg ; /* On-Chip Configuration Registers */
int Reserved1[(0x1000-(0x0 + sizeof ( AT91S_S1D13806_OnChipReg )))/4] ; /* Reserved */
AT91S_S1D13806_MediaPlug S1D13806_MediaPlug ; /* MediaPlug Configuration Registers */
int Reserved2[(0x100000-(0x1000 + sizeof ( AT91S_S1D13806_MediaPlug )))/4] ; /* Reserved */
AT91S_S1D13806_BitBLTReg S1D13806_BitBLTReg ; /* BitBLT Data Registers */
} AT91S_S1D13806_Desc, *AT91PS_S1D13806_Desc;
//////////////////////////////////////////////////////////////////////////////
/* Standard configurations definitions */
#define TFT_Display_Conf 0x0
#define CRT_Display_Conf 0x1
#define TFT_CRT_Display_Conf 0x2
/* Standard Display Resolution definitions */
#define Display_Def_0 0x0 /* 640 x 480 */
#define Display_Def_1 0x1 /* 800 x 600 */
/* Standard Character Definition definitions */
#define Char_Def_0 0x0 /* 8 x 16 */
/* Video Graphic Controller Display Memory Size definition */
#define S1D13806_DISP_MEM_SIZE 0x140000
/* Colors Word Masks */
#define BLUE_WORD_MASK 0x001F
#define GREEN_WORD_MASK 0x07E0
#define RED_WORD_MASK 0xF800
/*-------------------------------------------------------*/
/* S1D13806 Revision Code Register Bits Definition */
/*-------------------------------------------------------*/
#define S1D_PRD_MASK 0xFC /* Product Code Mask */
#define S1D_PRD_SHIFT 0x02 /* Product Code Shift */
#define S1D_REV_MASK 0x03 /* Revision Code Mask */
/*-------------------------------------------------------*/
/* S1D13806 Miscellaneous Register Bits Definition */
/*-------------------------------------------------------*/
#define S1D_RME 0x00 /* Register/Memory Access Enabled */
#define S1D_RMD 0x80 /* Register/Memory Access Disabled */
/*--------------------------------------*/
/* S1D13806 GPIOs Bits Definition */
/*--------------------------------------*/
#define S1D_GPIO0 (1 << 0) /* GPIO 0 */
#define S1D_GPIO1 (1 << 1) /* GPIO 1 */
#define S1D_GPIO2 (1 << 2) /* GPIO 2 */
#define S1D_GPIO3 (1 << 3) /* GPIO 3 */
#define S1D_GPIO4 (1 << 4) /* GPIO 4 */
#define S1D_GPIO5 (1 << 5) /* GPIO 5 */
#define S1D_GPIO6 (1 << 6) /* GPIO 6 */
#define S1D_GPIO7 (1 << 7) /* GPIO 7 */
#define S1D_GPIO8 (1 << 0) /* GPIO 8 */
#define S1D_GPIO9 (1 << 1) /* GPIO 9 */
#define S1D_GPIO10 (1 << 2) /* GPIO 10 */
#define S1D_GPIO11 (1 << 3) /* GPIO 11 */
#define S1D_GPIO12 (1 << 4) /* GPIO 12 */
/*-----------------------------------------------------------*/
/* S1D13806 Memory Clock Configuration Bits Definition */
/*-----------------------------------------------------------*/
#define S1D_MCK_DIV2 0x10 /* Memory Clock Divide by 2 Enable */
#define S1D_CLKI3_SRC 0x02 /* Memory Clock Source is CLKI3 */
/*-------------------------------------------------------------------------------------------------*/
/* S1D13806 Memory, LCD Pixel, CRT/TV Pixel & MediaPlug Clocks Configuration Bits Definition */
/*-------------------------------------------------------------------------------------------------*/
#define S1D_CLKI_SRC 0x00 /* Clock Source is CLKI */
#define S1D_BUSCLK_SRC 0x01 /* Clock Source is BUSCLK */
#define S1D_CLKI2_SRC 0x02 /* Clock Source is CLKI2 */
#define S1D_MCLK_SRC 0x03 /* Clock Source is MCLK */
#define S1D_SRC_DIV1 0x00 /* Clock Source is not divided */
#define S1D_SRC_DIV2 0x10 /* Clock Source is divided by 2 */
#define S1D_SRC_DIV3 0x20 /* Clock Source is divided by 3 */
#define S1D_SRC_DIV4 0x30 /* Clock Source is divided by 4 */
/*--------------------------------------------------*/
/* S1D13806 Wait State Select Bits Definition */
/*--------------------------------------------------*/
#define S1D_WS_0 0x00 /* Configuration 0 programmed */
#define S1D_WS_1 0x01 /* Configuration 1 programmed */
#define S1D_WS_2 0x02 /* Configuration 2 programmed */
/*-----------------------------------------------------*/
/* S1D13806 SDRAM Initialisation Bits Definition */
/*-----------------------------------------------------*/
#define S1D_SDRAM_INIT 0x80 /* SDRAM Initialisation Command */
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