startup.s

ARM外围FLASH 以及SDRAM烧写程序 完整的程序 可能对大家硬件编程有点帮助

                ; Enable EBI Chip Select assignments if necessary
                IF      EBI_CFG_SETUP != 0
                LDR     R0, =EBI_BASE

                LDR     R1, =EBI_CSA_Val
                STR     R1, [R0, #EBI_CSA_OFS]
                LDR     R1, =EBI_CFGR_Val
                STR     R1, [R0, #EBI_CFGR_OFS]
                ENDIF

                ; Setup SDRAM Controller if enabled
                IF      :DEF:NO_SDRAM_INIT
                ELSE
                IF      SDRAMC_SETUP != 0

                ; Setup Parallel Input/Output C Registers
                ; for driving SDRAM lines
                LDR     R0, =PIOC_BASE
                LDR     R1, =0xFFFF0000  
                STR     R1, [R0, #PIO_PDR_OFS]

                LDR     R0, =SDRAMC_BASE
                LDR     R2, =EBI_CS1_ADDRESS
                MOV     R3, #0

                ; Write All Banks Precharge Command to SDRAM
                MOV     R1, #PRCGALL_CMD
                STR     R1, [R0, #SDRAMC_MR_OFS]
                STR     R3, [R2, #0]

                ; Provide 8 Auto Refresh to SDRAM
                MOV     R1, #RFSH_CMD
                STR     R1, [R0, #SDRAMC_MR_OFS]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]
                STR     R3, [R2, #0]

                ; Write a Load Mode Register Command to SDRAM
                MOV     R1, #LMR_CMD
                STR     R1, [R0, #SDRAMC_MR_OFS]
                STR     R3, [R2, #0x80]

                ; Setup Refresh Timer Register
                LDR     R1, =SDRAMC_TR_Val
                STR     R1, [R0, #SDRAMC_TR_OFS]
                STR     R3, [R2, #0]

                ; Setup SDRAM Controller Registers
                LDR     R1, =SDRAMC_CR_Val
                STR     R1, [R0, #SDRAMC_CR_OFS]

                LDR     R1, =SDRAMC_SRR_Val
                STR     R1, [R0, #SDRAMC_SRR_OFS]
                LDR     R1, =SDRAMC_IER_Val
                STR     R1, [R0, #SDRAMC_IER_OFS]
                ENDIF

                ENDIF   ; of IF      :DEF:NO_SDRAM_INIT

                ; Setup Burst Flash Controller if enabled
                IF      BFC_SETUP != 0

                ; Setup Parallel Input/Output C Registers
                ; for driving Burst Flash
                LDR     R0, =PIOC_BASE
                MOV     R1, #0x7F  
                STR     R1, [R0, #PIO_PDR_OFS]

                ; Setup Burst Flash Controller Registers
                LDR     R0, =BFC_BASE

                LDR     R1, =BFC_MR_Val
                STR     R1, [R0, #BFC_MR_OFS]
                ENDIF

                ENDIF   ; of IF EBI_SETUP != 0


; Setup Power Management Controller (PMC)

                IF      :DEF:NO_PMC_INIT
                ELSE
                IF      PMC_SETUP != 0
                LDR     R0, =PMC_BASE

                ; System Clock Enable
                LDR     R1, =PMC_SCER_Val
                STR     R1, [R0, #PMC_SCER_OFS]

                ; Peripheral Clock Enable
                LDR     R1, =PMC_PCER_Val
                STR     R1, [R0, #PMC_PCER_OFS]

                ; Setup Main Oscillator
                IF      (CKGR_MOR_Val:AND:PMC_MOSCEN) != 0
                LDR     R1, =CKGR_MOR_Val
                STR     R1, [R0, #CKGR_MOR_OFS]

                ; Wait until Main Oscillator is stabilized
MOSCS_Loop      LDR     R2, [R0, #PMC_SR_OFS]
                ANDS    R2, R2, #PMC_MOSCS
                BEQ     MOSCS_Loop
                ENDIF

                ; Setup the PLL A
                IF      (CKGR_PLLAR_Val:AND:PMC_MUL) != 0  
                LDR     R1, =CKGR_PLLAR_Val
                STR     R1, [R0, #CKGR_PLLAR_OFS]

                ; Wait until PLL A is stabilized
PLLA_Loop       LDR     R2, [R0, #PMC_SR_OFS]
                ANDS    R2, R2, #PMC_LOCKA
                BEQ     PLLA_Loop
                ENDIF

                ; Setup the PLL B
                IF      (CKGR_PLLBR_Val:AND:PMC_MUL) != 0  
                LDR     R1, =CKGR_PLLBR_Val
                STR     R1, [R0, #CKGR_PLLBR_OFS]

                ; Wait until PLL B is stabilized
PLLB_Loop       LDR     R2, [R0, #PMC_SR_OFS]
                ANDS    R2, R2, #PMC_LOCKB
                BEQ     PLLB_Loop
                ENDIF

                ; Setup the Master Clock and the Processor Clock
                LDR     R1, =PMC_MCKR_Val
                STR     R1, [R0, #PMC_MCKR_OFS]

                ; Wait until Main Master Clock is ready
MCKR_Loop       LDR     R2, [R0, #PMC_SR_OFS]
                ANDS    R2, R2, #PMC_MCKRDY
                BEQ     MCKR_Loop

                ; Setup Programmable Clock Register 0
                LDR     R1, =PMC_PCK0_Val
                STR     R1, [R0, #PMC_PCK0_OFS]

                ; Setup Programmable Clock Register 1
                LDR     R1, =PMC_PCK1_Val
                STR     R1, [R0, #PMC_PCK1_OFS]

                ; Setup Programmable Clock Register 2
                LDR     R1, =PMC_PCK2_Val
                STR     R1, [R0, #PMC_PCK2_OFS]

                ; Setup Programmable Clock Register 3
                LDR     R1, =PMC_PCK3_Val
                STR     R1, [R0, #PMC_PCK3_OFS]
                ENDIF

                ENDIF   ; of IF      :DEF:NO_PMC_INIT

; Enable USART2

                LDR     R0, =PIOA_BASE  ; Open PIO for USART2
                MOV     R1, #0xC00000
                STR     R1, [R0, #0x04]

                LDR     R0, =PMC_BASE   ; Open USART2 Clock and TC2
                LDR     R1, =0x80100
                STR     R1, [R0, #0x10]


; Copy Exception Vectors to Internal RAM

                IF      :DEF:RAM_INTVEC
                ADR     R8, Vectors     ; Source
                LDR     R9, =RAM_BASE   ; Destination
                LDMIA   R8!, {R0-R7}    ; Load Vectors 
                STMIA   R9!, {R0-R7}    ; Store Vectors 
                LDMIA   R8!, {R0-R7}    ; Load Handler Addresses 
                STMIA   R9!, {R0-R7}    ; Store Handler Addresses
                ENDIF


; Remap on-chip RAM to address 0

                IF      :DEF:REMAP
                LDR     R0, =MC_BASE
                MOV     R1, #1
                STR     R1, [R0, #MC_RCR_OFS]   ; Remap
                ENDIF

; Cache Setup
                IF      CACHE_SETUP != 0
                MRC     p15, 0, R0, c1, c0, 0   ; Enable Instruction Cache
                ORR     R0, R0, #ICACHE_ENABLE
                MCR     p15, 0, R0, c1, c0, 0
                ENDIF


; Setup Stack for each mode

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size

; Execute C function: AT91F_LowLevelInit (...)

                IMPORT  AT91F_LowLevelInit

; Execute AT91F_LowLevelInit function
                LDR     R0, = AT91F_LowLevelInit
                MOV     LR, PC
                BX      R0


; Enter the C code

                IMPORT  __main
                LDR     R0, =__main
                BX      R0


; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR


                END