startup.s

ARM外围FLASH 以及SDRAM烧写程序 完整的程序 可能对大家硬件编程有点帮助

;//   </h>
;//
;//   <h> Peripheral Clock Enable Register (PMC_PCER)
;//     <o2.2>      PID2: Parallel IO Controller A Enable
;//     <o2.3>      PID3: Parallel IO Controller B Enable
;//     <o2.4>      PID4: Parallel IO Controller C Enable
;//     <o2.5>      PID5: Parallel IO Controller D Enable
;//     <o2.6>      PID6: USART0 Enable
;//     <o2.7>      PID7: USART1 Enable
;//     <o2.8>      PID8: USART2 Enable
;//     <o2.9>      PID9: USART3 Enable
;//     <o2.10>     PID10: Multimedia Card Interface Enable
;//     <o2.11>     PID11: USB Device Port Enable
;//     <o2.12>     PID12: Two-Wire Interface Enable
;//     <o2.13>     PID13: Serial Peripheral Interface Enable
;//     <o2.14>     PID14: Serial Synchronous Controller 0 Enable
;//     <o2.15>     PID15: Serial Synchronous Controller 1 Enable
;//     <o2.16>     PID16: Serial Synchronous Controller 2 Enable
;//     <o2.17>     PID17: Timer Counter 0 Enable
;//     <o2.18>     PID18: Timer Counter 1 Enable
;//     <o2.19>     PID19: Timer Counter 2 Enable
;//     <o2.20>     PID20: Timer Counter 3 Enable
;//     <o2.21>     PID21: Timer Counter 4 Enable
;//     <o2.22>     PID22: Timer Counter 5 Enable
;//     <o2.23>     PID23: USB Host Port Enable
;//     <o2.24>     PID24: Ethernet MAC Enable
;//     <o2.25>     PID25: Advanced Interrupt Controller (IRQ0) Enable
;//     <o2.26>     PID26: Advanced Interrupt Controller (IRQ1) Enable
;//     <o2.27>     PID27: Advanced Interrupt Controller (IRQ2) Enable
;//     <o2.28>     PID28: Advanced Interrupt Controller (IRQ3) Enable
;//     <o2.29>     PID29: Advanced Interrupt Controller (IRQ4) Enable
;//     <o2.30>     PID30: Advanced Interrupt Controller (IRQ5) Enable
;//     <o2.31>     PID31: Advanced Interrupt Controller (IRQ6) Enable
;//   </h>
;//
;//   <h> Main Oscillator Register (CKGR_MOR)
;//     <o3.0>      MOSCEN: Main Oscillator Enable
;//     <o3.8..15>  OSCOUNT: Main Oscillator Startup Time <0-255>
;//   </h>
;//
;//   <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
;//                   <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
;//     <o4.0..7>   DIVA: PLL Divider A <0-255>
;//                   <i> 0        - Divider output is 0
;//                   <i> 1        - Divider is bypassed
;//                   <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
;//     <o4.8..13>  PLLACOUNT: PLL A Counter <0-63>
;//                   <i> Number of Slow Clocks before the LOCKA bit is set in 
;//                   <i> PMC_SR after CKGR_PLLAR is written
;//     <o4.14..15> OUTA: PLL A Clock Frequency Range
;//                   <0=> 80 .. 160MHz   <1=> Reserved
;//                   <2=> 150 .. 240MHz  <3=> Reserved
;//     <o4.16..26> MULA: PLL A Multiplier <0-2047>
;//                   <i> 0         - The PLL A is deactivated
;//                   <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input 
;//                   <i>             frequency multiplied by MULA + 1
;//   </h>
;//
;//   <h> Clock Generator Phase Locked Loop B Register (CKGR_PLLBR)
;//                   <i> PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1)
;//     <o5.0..7>   DIVB: PLL Divider B <0-255>
;//                   <i> 0        - Divider output is 0
;//                   <i> 1        - Divider is bypassed
;//                   <i> 2 .. 255 - Divider output is the Main Clock divided by DIVB
;//     <o5.8..13>  PLLBCOUNT: PLL B Counter <0-63>
;//                   <i> Number of Slow Clocks before the LOCKB bit is set in 
;//                   <i> PMC_SR after CKGR_PLLBR is written
;//     <o5.14..15> OUTB: PLL B Clock Frequency Range
;//                   <0=> 80 .. 160MHz   <1=> Reserved
;//                   <2=> 150 .. 240MHz  <3=> Reserved
;//     <o5.16..26> MULB: PLL B Multiplier <0-2047>
;//                   <i> 0         - The PLL B is deactivated
;//                   <i> 1 .. 2047 - The PLL B Clock frequency is the PLL a input 
;//                   <i>             frequency multiplied by MULB + 1
;//     <o5.28>     USB_96M: Divider by 2 Enable
;//                   <i> 0 - USB ports = PLL B Clock, PLL B Clock must be 48MHz
;//                   <i> 1 - USB ports = PLL B Clock / 2, PLL B Clock must be 96MHz
;//   </h>
;//
;//   <h> Master Clock Register (CKGR_MCKR)
;//     <o6.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o6.2..4>   PRES: Master Clock Prescaler
;//                   <0=> Clock        <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//     <o6.8..9>   MDIV: Master Clock Division
;//                   <0=> Processor Clock = Master Clock
;//                   <1=> Processor Clock = Master Clock / 2
;//                   <2=> Processor Clock = Master Clock / 3
;//                   <3=> Processor Clock = Master Clock / 4
;//   </h>
;//
;//   <h> Programmable Clock Register 0 (PMC_PCK0)
;//     <o7.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o7.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> Clock        <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 1 (PMC_PCK1)
;//     <o8.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o8.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 2 (PMC_PCK2)
;//     <o9.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o9.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 3 (PMC_PCK3)
;//     <o10.0..1>  CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o10.2..4>  PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;// </e>
PMC_SETUP       EQU     1
PMC_SCER_Val    EQU     0x00000001
PMC_PCER_Val    EQU     0x00000018
CKGR_MOR_Val    EQU     0x0000FF01
CKGR_PLLAR_Val  EQU     0x00000000
CKGR_PLLBR_Val  EQU     0x100F3E05
PMC_MCKR_Val    EQU     0x00000003
PMC_PCK0_Val    EQU     0x00000000
PMC_PCK1_Val    EQU     0x00000000
PMC_PCK2_Val    EQU     0x00000000
PMC_PCK3_Val    EQU     0x00000000


; Cache

; Constants
ICACHE_ENABLE   EQU     (1<<12)         ; Instruction Cache Enable Value

;// <e> Instruction Cache Enable
;// </e>
CACHE_SETUP     EQU     1


                PRESERVE8
                

; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    RESET, CODE, READONLY
                ARM

; Define the entry point

               EXPORT   __ENTRY
__ENTRY


; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC,Reset_Addr         
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                NOP                     ; Reserved Vector
;               LDR     PC,IRQ_Addr     
                LDR     PC,[PC,#-0xF20] ; Vector From AIC_IVR
;               LDR     PC,FIQ_Addr
                LDR     PC,[PC,#-0xF20] ; Vector From AIC_FVR

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0               ; Reserved Address
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
IRQ_Handler     B       IRQ_Handler
FIQ_Handler     B       FIQ_Handler


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   


; Setup External Bus Interface (EBI)

                IF      EBI_SETUP != 0

                ; Setup Static Memory Controller if enabled
                LDR     R0, =SMC_BASE

                IF      SMC_CSR0_SETUP != 0
                LDR     R1, =SMC_CSR0_Val
                STR     R1, [R0, #SMC_CSR0_OFS]
                ENDIF
                IF      SMC_CSR1_SETUP != 0
                LDR     R1, =SMC_CSR1_Val
                STR     R1, [R0, #SMC_CSR1_OFS]
                ENDIF
                IF      SMC_CSR2_SETUP != 0
                LDR     R1, =SMC_CSR2_Val
                STR     R1, [R0, #SMC_CSR2_OFS]
                ENDIF
                IF      SMC_CSR3_SETUP != 0
                LDR     R1, =SMC_CSR3_Val
                STR     R1, [R0, #SMC_CSR3_OFS]
                ENDIF
                IF      SMC_CSR4_SETUP != 0
                LDR     R1, =SMC_CSR4_Val
                STR     R1, [R0, #SMC_CSR4_OFS]
                ENDIF
                IF      SMC_CSR5_SETUP != 0
                LDR     R1, =SMC_CSR5_Val
                STR     R1, [R0, #SMC_CSR5_OFS]
                ENDIF
                IF      SMC_CSR6_SETUP != 0
                LDR     R1, =SMC_CSR6_Val
                STR     R1, [R0, #SMC_CSR6_OFS]
                ENDIF
                IF      SMC_CSR7_SETUP != 0
                LDR     R1, =SMC_CSR7_Val
                STR     R1, [R0, #SMC_CSR7_OFS]
                ENDIF