startup.s

ARM外围FLASH 以及SDRAM烧写程序 完整的程序 可能对大家硬件编程有点帮助

;/*****************************************************************************/
;/* Startup.S: Startup file for Atmel AT91RM9200 device series                */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>                          */ 
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.                   */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved.               */
;/* This software may only be used under the terms of a valid, current,       */
;/* end user licence from KEIL for a compatible version of KEIL software      */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/


;/*
; *  The Startup.S code is executed after CPU Reset. This file may be 
; *  translated with the following SET symbols. In uVision these SET 
; *  symbols are entered under Options - ASM - Define.
; *
; *  REMAP: when set the startup code remaps exception vectors from
; *  on-chip RAM to address 0.
; *
; *  RAM_INTVEC: when set the startup code copies exception vectors 
; *  from on-chip Flash to on-chip RAM.
; *
; *  NO_SDRAM_INIT: when set the SDRAM controller is not initialized in startup
; *  and it is used when SDRAM controller is initialized from debugger 
; *  enviroment (using the debug script).
; *
; *  NO_PMC_INIT: when set the Power Management Controller and system clock 
; *  are not initialized in startup and it is used when PLL is initialized from 
; *  debugger enviroment (using the debug script).
; */


; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F

I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled


; Internal Memory Base Addresses
FLASH_BASE      EQU     0x00100000   
RAM_BASE        EQU     0x00200000

;// <h> Stack Configuration (Stack Sizes in Bytes)
;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
;// </h>

UND_Stack_Size  EQU     0x00000000
SVC_Stack_Size  EQU     0x00000008
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000080
USR_Stack_Size  EQU     0x00000400

Stack_Size      EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                         FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size

Stack_Top       EQU     Stack_Mem + Stack_Size


;// <h> Heap Configuration
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>

Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size


; Parallel Input/Output Controller (PIO) User Interface
PIOA_BASE       EQU     0xFFFFF400      ; PIO A Base Address
PIOB_BASE       EQU     0xFFFFF600      ; PIO B Base Address
PIOC_BASE       EQU     0xFFFFF800      ; PIO C Base Address
PIOD_BASE       EQU     0xFFFFFA00      ; PIO D Base Address
PIO_PER_OFS     EQU     0x00            ; PIO Enable Register     Address Offset
PIO_PDR_OFS     EQU     0x04            ; PIO Disable Register    Address Offset
PIO_OER_OFS     EQU     0x10            ; PIO Output Enable Reg   Address Offset
PIO_ODR_OFS     EQU     0x14            ; PIO Output Disable Reg  Address Offset
PIO_MDER_OFS    EQU     0x50            ; PIO Multi-Driver En Reg Address Offset
PIO_MDDR_OFS    EQU     0x54            ; PIO Multi-Driver Ds Reg Address Offset
PIO_PUDR_OFS    EQU     0x60            ; PIO Pull-up Disable Reg Address Offset
PIO_PUER_OFS    EQU     0x64            ; PIO Pull-up Enable Reg  Address Offset
PIO_ASR_OFS     EQU     0x70            ; PIO Periph A Select Reg Address Offset
PIO_BSR_OFS     EQU     0x74            ; PIO Periph B Select Reg Address Offset


; Memory Control (MC) User Interface
;  |- External Bus Interface (EBI) User Interface
;      |- Static Memory Controller (SMC) User Interface
;      |- SDRAM Controller (SDRAMC) User Interface
;      |- Burst Flash Controller (BFC) User Interface
MC_BASE         EQU     0xFFFFFF00      ; MC Base Address
MC_RCR_OFS      EQU     0x00            ; Remap Control Reg       Address Offset
MC_ASR_OFS      EQU     0x04            ; Abort Status Register   Address Offset
MC_AASR_OFS     EQU     0x08            ; Abort Adress Status Reg Address Offset

; External Bus Interface (EBI) User Interface
EBI_BASE        EQU     0xFFFFFF60      ; EBI Base Address
EBI_CSA_OFS     EQU     0x00            ; Chip Select Assign Reg  Address Offset
EBI_CFGR_OFS    EQU     0x04            ; Configuration Register  Address Offset

; Static Memory Controller (SMC) User Interface
SMC_BASE        EQU     0xFFFFFF70      ; SMC Base Address
SMC_CSR0_OFS    EQU     0x00            ; Chip Select 0 Reg       Address Offset
SMC_CSR1_OFS    EQU     0x04            ; Chip Select 1 Reg       Address Offset
SMC_CSR2_OFS    EQU     0x08            ; Chip Select 2 Reg       Address Offset
SMC_CSR3_OFS    EQU     0x0C            ; Chip Select 3 Reg       Address Offset
SMC_CSR4_OFS    EQU     0x10            ; Chip Select 4 Reg       Address Offset
SMC_CSR5_OFS    EQU     0x14            ; Chip Select 5 Reg       Address Offset
SMC_CSR6_OFS    EQU     0x18            ; Chip Select 6 Reg       Address Offset
SMC_CSR7_OFS    EQU     0x1C            ; Chip Select 7 Reg       Address Offset

; Constants
EBI_CS0_ADDRESS EQU     0x10000000      ; Start of memory addressed by CS0
EBI_CS1_ADDRESS EQU     0x20000000      ; Start of memory addressed by CS1
EBI_CS2_ADDRESS EQU     0x30000000      ; Start of memory addressed by CS2
EBI_CS3_ADDRESS EQU     0x40000000      ; Start of memory addressed by CS3
EBI_CS4_ADDRESS EQU     0x50000000      ; Start of memory addressed by CS4
EBI_CS5_ADDRESS EQU     0x60000000      ; Start of memory addressed by CS5
EBI_CS6_ADDRESS EQU     0x70000000      ; Start of memory addressed by CS6
EBI_CS7_ADDRESS EQU     0x80000000      ; Start of memory addressed by CS7

; SDRAM Controller (SDRAMC) User Interface
SDRAMC_BASE     EQU     0xFFFFFF90      ; SDRAMC Base Address
SDRAMC_MR_OFS   EQU     0x00            ; Mode Register          Address Offsett
SDRAMC_TR_OFS   EQU     0x04            ; Refresh Timer Register Address Offsett
SDRAMC_CR_OFS   EQU     0x08            ; Configuration Register Address Offsett
SDRAMC_SRR_OFS  EQU     0x0C            ; Self Refresh Register  Address Offsett
SDRAMC_LPR_OFS  EQU     0x10            ; Low Power Register     Address Offsett
SDRAMC_IER_OFS  EQU     0x14            ; Interrupt Enable Reg   Address Offsett
SDRAMC_IDR_OFS  EQU     0x18            ; Interrupt Disable Reg  Address Offsett
SDRAMC_IMR_OFS  EQU     0x1C            ; Interrupt Mask Reg     Address Offsett
SDRAMC_ISR_OFS  EQU     0x20            ; Interrupt Status Reg   Address Offsett

; Constants
NORMAL_CMD      EQU     0x00            ; SDRAM Normal Mode
NOP_CMD         EQU     0x01            ; SDRAM NOP Command
PRCGALL_CMD     EQU     0x02            ; SDRAM All Banks Precharge Command
LMR_CMD         EQU     0x03            ; SDRAM Load Mode Register Command
RFSH_CMD        EQU     0x04            ; SDRAM Refresh Command

; Burst Flash Controller (BFC) User Interface
BFC_BASE        EQU     0xFFFFFFC0      ; BFC Base Address
BFC_MR_OFS      EQU     0x00            ; Mode Register          Address Offset

;// <e> External Bus Interface (EBI)
EBI_SETUP       EQU     1

;//   <h> Static Memory Controller Chip Select Registers
;//     <e> Chip Select Register 0 (SMC_CSR0)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                    <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR0_SETUP  EQU     0x00000001
SMC_CSR0_Val    EQU     0x00003284

;//     <e> Chip Select Register 1 (SMC_CSR1)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR1_SETUP  EQU     0x00000000
SMC_CSR1_Val    EQU     0x00000000

;//     <e> Chip Select Register 2 (SMC_CSR2)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR2_SETUP  EQU     0x00000000
SMC_CSR2_Val    EQU     0x77003A8A

;//     <e> Chip Select Register 3 (SMC_CSR3)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR3_SETUP  EQU     0x00000000
SMC_CSR3_Val    EQU     0x00000000

;//     <e> Chip Select Register 4 (SMC_CSR4)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled