interconn.iml,1

于博士cadence视频配套工程文件

*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL7An225W8000
+L7An225W8000 0 1.21634e-013
CL7An90W8000
+L7An90W8000 0 1.21634e-013
RLL1A0W8000_L7An225W8000 L1A0W8000 L7An225W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7An90W8000 L1A0W8000 L7An90W8000 1e-7 L=1.64454e-009
RLL7An225W8000_L7An90W8000 L7An225W8000 L7An90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000L7An90W8000_FST_218
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A180W8000_FST_8749 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A180W8000_FST_8749
+L1A0W8000 L7A180W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A180W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.00174125 0.00174125) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A180W8000 180 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A180W8000
+L7A180W8000 0 1.82452e-013
RLL1A0W8000_L7A180W8000 L1A0W8000 L7A180W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A180W8000_FST_8749
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A0W8000_FST_2605 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A0W8000_FST_2605
+L1A0W8000 L7A0W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A0W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A0W8000 0 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A0W8000
+L7A0W8000 0 1.82452e-013
RLL1A0W8000_L7A0W8000 L1A0W8000 L7A0W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A0W8000_FST_2605
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An45W8000L7A90W8000_FST_21 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An45W8000L7A90W8000_FST_21
+L1A0W8000 L7An45W8000 L7A90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An45W8000 L7A90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An45W8000 -45 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
+ trace( L7A90W8000 90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL7An45W8000
+L7An45W8000 0 1.21634e-013
CL7A90W8000
+L7A90W8000 0 1.21634e-013
RLL1A0W8000_L7An45W8000 L1A0W8000 L7An45W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7A90W8000 L1A0W8000 L7A90W8000 1e-7 L=1.64454e-009
RLL7An45W8000_L7A90W8000 L7An45W8000 L7A90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An45W8000L7A90W8000_FST_21
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A270W8000L7A90W8000_FST_302 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A270W8000L7A90W8000_FST_302
+L1A0W8000 L1A270W8000 L7A90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L1A270W8000 L7A90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L1A270W8000 270 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A90W8000 90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL1A270W8000
+L1A270W8000 0 1.21634e-013
CL7A90W8000
+L7A90W8000 0 1.21634e-013
RLL1A0W8000_L1A270W8000 L1A0W8000 L1A270W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7A90W8000 L1A0W8000 L7A90W8000 1e-7 L=1.64454e-009
RLL1A270W8000_L7A90W8000 L1A270W8000 L7A90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A270W8000L7A90W8000_FST_302
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A135W8000_FST_7940 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A135W8000_FST_7940
+L1A0W8000 L7A135W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A135W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.00141189 0.00141189) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A135W8000 135 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A135W8000
+L7A135W8000 0 1.82452e-013
RLL1A0W8000_L7A135W8000 L1A0W8000 L7A135W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A135W8000_FST_7940
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W12000L7An180W12000_FST_7303 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W12000L7An180W12000_FST_7303
+L1A0W12000 L7An180W12000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W12000 L7An180W12000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0012096 0.0012096) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0012096 0.0012096) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W12000 0 rectangle(5.959e+007 0.0 0.00131064 0.0003048 0.00134112))
+ trace( L7An180W12000 -180 rectangle(5.959e+007 0.0 0 0.0003048 3.048e-005))
*FormulaModel via circuits
CL1A0W12000
+L1A0W12000 0 1.82452e-013
CL7An180W12000
+L7An180W12000 0 1.82452e-013
RLL1A0W12000_L7An180W12000 L1A0W12000 L7An180W12000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W12000L7An180W12000_FST_7303
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W12000L7A135W12000_FST_104 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W12000L7A135W12000_FST_104
+L1A0W12000 L7A135W12000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W12000 L7A135W12000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0012096 0.0012096) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0012096 0.0012096) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W12000 0 rectangle(5.959e+007 0.0 0.00131064 0.0003048 0.00134112))
+ trace( L7A135W12000 135 rectangle(5.959e+007 0.0 0 0.0003048 3.048e-005))
*FormulaModel via circuits
CL1A0W12000
+L1A0W12000 0 1.82452e-013
CL7A135W12000
+L7A135W12000 0 1.82452e-013
RLL1A0W12000_L7A135W12000 L1A0W12000 L7A135W12000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W12000L7A135W12000_FST_104
" ) ) ) 
 (MultiTrace 
  (MTL_1S_2R_9463 
   (IDL ".subckt MTL_1S_2R_9463 
+X1 X3 0 
+X2 X4 0 


.layerstack Layerstack3
+shield( 3.048e-005 1 0 )
+dielectric( 0.000508 4.5 0.035 )
.crosssection
+rectangle ( 5.959e+007 0 0.000508 0.0002032 0.00053848 )
+rectangle ( 5.959e+007 0.0004064 0.000508 0.0006096 0.00053848 )
+Length=length
.rlgc RLGCMTL_1S_2R_9463 ( Length=length N=2 )
.C 0
+ 6.421000e-011 -1.845800e-011 
+ -1.845800e-011 6.421000e-011 
.L 0
+ 5.537500e-007 2.113200e-007 
+ 2.113200e-007 5.537500e-007 
.G 0
+ 0.000000e+000 0.000000e+000 
+ 0.000000e+000 0.000000e+000 
.R 0
+ 2.709500e+000 0.000000e+000 
+ 0.000000e+000 2.709500e+000 
.endrlgc RLGCMTL_1S_2R_9463

**The Characteristic Modal Delay, Admittance and
**Impedance Matrices of these Transmission Lines:

*Delay Matrix.
*Td 0 (n=2)
*  5.916400e-009 0.000000e+000 
*  0.000000e+000 5.320500e-009 

*Admittance Matrix.
*Y 0 (n=2)
* 1.163500e-002 -3.902200e-003 
* -3.902200e-003 1.163500e-002 

*Impedance Matrix.
*Z 0 (n=2)
*  9.683700e+001 3.247700e+001 
*  3.247700e+001 9.683700e+001 

*Odd Mode Impedances, 2*(z11-z12).
* Z(odd)  = 1.287200e+002
*Even Mode Impedances, (z11+z12)/2.
* Z(even) = 6.465700e+001


**The Near-End Crosstalk Coefficent of these Transmission
**Lines based on Near-End Resistance=50 ohm assumption:

*Near-End Crosstalk Coefficent Matrix, Z0*Inv(R+Z0).
*  0 (n=2)
*  6.419700e-001 7.918700e-002 
*  7.918700e-002 6.419700e-001 
.ends MTL_1S_2R_9463
" ) 
   (KSPICE "DATAPOINTS RLGC MTL_1S_2R_9463
FREQUENCY=0
CMATRIX
 6.421000e-011 -1.845800e-011
 -1.845800e-011 6.421000e-011
LMATRIX
 5.537500e-007 2.113200e-007
 2.113200e-007 5.537500e-007
GMATRIX
 0.000000e+000 0.000000e+000
 0.000000e+000 0.000000e+000
RMATRIX
 2.709500e+000 0.000000e+000
 0.000000e+000 2.709500e+000
END RLGC
" ) 
   (Frequency 0 ) ) 
  (MTL_1S_2R_9464 
   (IDL ".subckt MTL_1S_2R_9464 
+X1 X3 0 
+X2 X4 0 


.layerstack Layerstack1
+dielectric( 0.000508 4.5 0.035 )
+shield( 3.048e-005 1 0 )
.crosssection
+rectangle ( 5.959e+007 0 -3.048e-005 0.0002032 0 )
+rectangle ( 5.959e+007 0.0004064 -3.048e-005 0.0006096 0 )
+Length=length
.rlgc RLGCMTL_1S_2R_9464 ( Length=length N=2 )
.C 0
+ 6.421000e-011 -1.845800e-011 
+ -1.845800e-011 6.421000e-011 
.L 0
+ 5.537500e-007 2.113200e-007 
+ 2.113200e-007 5.537500e-007 
.G 0
+ 0.000000e+000 0.000000e+000 
+ 0.000000e+000 0.000000e+000 
.R 0
+ 2.709500e+000 0.000000e+000 
+ 0.000000e+000 2.709500e+000 
.endrlgc RLGCMTL_1S_2R_9464

**The Characteristic Modal Delay, Admittance and
**Impedance Matrices of these Transmission Lines:

*Delay Matrix.
*Td 0 (n=2)
*  5.916400e-009 0.000000e+000 
*  0.000000e+000 5.320500e-009 

*Admittance Matrix.
*Y 0 (n=2)
* 1.163500e-002 -3.902200e-003 
* -3.902200e-003 1.163500e-002 

*Impedance Matrix.
*Z 0 (n=2)
*  9.683700e+001 3.247700e+001 
*  3.247700e+001 9.683700e+001 

*Odd Mode Impedances, 2*(z11-z12).
* Z(odd)  = 1.287200e+002
*Even Mode Impedances, (z11+z12)/2.
* Z(even) = 6.465700e+001


**The Near-End Crosstalk Coefficent of these Transmission
**Lines based on Near-End Resistance=50 ohm assumption:

*Near-End Crosstalk Coefficent Matrix, Z0*Inv(R+Z0).
*  0 (n=2)
*  6.419700e-001 7.918700e-002 
*  7.918700e-002 6.419700e-001 
.ends MTL_1S_2R_9464
" ) 
   (KSPICE "DATAPOINTS RLGC MTL_1S_2R_9464
FREQUENCY=0
CMATRIX
 6.421000e-011 -1.845800e-011
 -1.845800e-011 6.421000e-011
LMATRIX
 5.537500e-007 2.113200e-007
 2.113200e-007 5.537500e-007
GMATRIX
 0.000000e+000 0.000000e+000
 0.000000e+000 0.000000e+000
RMATRIX
 2.709500e+000 0.000000e+000
 0.000000e+000 2.709500e+000
END RLGC
" ) 
   (Frequency 0 ) ) ) 
 (LibraryVersion 136.2 ) )