interconn.iml,1

于博士cadence视频配套工程文件

" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000_FST_1381 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000_FST_1381
+L1A0W8000 L7An225W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An225W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.00143933 0.00143933) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.00143933 0.00143933) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An225W8000 -225 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An225W8000
+L7An225W8000 0 1.82452e-013
RLL1A0W8000_L7An225W8000 L1A0W8000 L7An225W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000_FST_1381
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A135W8000_FST_9458 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A135W8000_FST_9458
+L1A0W8000 L7A135W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A135W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A135W8000 135 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A135W8000
+L7A135W8000 0 1.82452e-013
RLL1A0W8000_L7A135W8000 L1A0W8000 L7A135W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A135W8000_FST_9458
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000L7A45W8000_FST_5359 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000L7A45W8000_FST_5359
+L1A0W8000 L7An90W8000 L7A45W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An90W8000 L7A45W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An90W8000 -90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
+ trace( L7A45W8000 45 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL7An90W8000
+L7An90W8000 0 1.21634e-013
CL7A45W8000
+L7A45W8000 0 1.21634e-013
RLL1A0W8000_L7An90W8000 L1A0W8000 L7An90W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7A45W8000 L1A0W8000 L7A45W8000 1e-7 L=1.64454e-009
RLL7An90W8000_L7A45W8000 L7An90W8000 L7A45W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000L7A45W8000_FST_5359
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An45W8000_FST_3464 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An45W8000_FST_3464
+L1A0W8000 L7An45W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An45W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An45W8000 -45 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An45W8000
+L7An45W8000 0 1.82452e-013
RLL1A0W8000_L7An45W8000 L1A0W8000 L7An45W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An45W8000_FST_3464
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An270W8000L7An90W8000_FST_6212 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An270W8000L7An90W8000_FST_6212
+L1A0W8000 L7An270W8000 L7An90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An270W8000 L7An90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An270W8000 -270 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
+ trace( L7An90W8000 -90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL7An270W8000
+L7An270W8000 0 1.21634e-013
CL7An90W8000
+L7An90W8000 0 1.21634e-013
RLL1A0W8000_L7An270W8000 L1A0W8000 L7An270W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7An90W8000 L1A0W8000 L7An90W8000 1e-7 L=1.64454e-009
RLL7An270W8000_L7An90W8000 L7An270W8000 L7An90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An270W8000L7An90W8000_FST_6212
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An135W8000_FST_7654 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An135W8000_FST_7654
+L1A0W8000 L7An135W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An135W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An135W8000 -135 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An135W8000
+L7An135W8000 0 1.82452e-013
RLL1A0W8000_L7An135W8000 L1A0W8000 L7An135W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An135W8000_FST_7654
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A90W8000_FST_5953 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A90W8000_FST_5953
+L1A0W8000 L7A90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A90W8000 90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A90W8000
+L7A90W8000 0 1.82452e-013
RLL1A0W8000_L7A90W8000 L1A0W8000 L7A90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A90W8000_FST_5953
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A180W8000_FST_1364 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A180W8000_FST_1364
+L1A0W8000 L7A180W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A180W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A180W8000 180 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A180W8000
+L7A180W8000 0 1.82452e-013
RLL1A0W8000_L7A180W8000 L1A0W8000 L7A180W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A180W8000_FST_1364
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000_FST_2214 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000_FST_2214
+L1A0W8000 L7An225W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An225W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An225W8000 -225 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An225W8000
+L7An225W8000 0 1.82452e-013
RLL1A0W8000_L7An225W8000 L1A0W8000 L7An225W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000_FST_2214
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A225W8000_FST_8832 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A225W8000_FST_8832
+L1A0W8000 L7A225W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7A225W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A225W8000 225 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7A225W8000
+L7A225W8000 0 1.82452e-013
RLL1A0W8000_L7A225W8000 L1A0W8000 L7A225W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7A225W8000_FST_8832
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A135W8000L7An90W8000_FST_3534 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A135W8000L7An90W8000_FST_3534
+L1A0W8000 L1A135W8000 L7An90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L1A135W8000 L7An90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L1A135W8000 135 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An90W8000 -90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL1A135W8000
+L1A135W8000 0 1.21634e-013
CL7An90W8000
+L7An90W8000 0 1.21634e-013
RLL1A0W8000_L1A135W8000 L1A0W8000 L1A135W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7An90W8000 L1A0W8000 L7An90W8000 1e-7 L=1.64454e-009
RLL1A135W8000_L7An90W8000 L1A135W8000 L7An90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A135W8000L7An90W8000_FST_3534
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A180W8000L7A90W8000_FST_6654 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A180W8000L7A90W8000_FST_6654
+L1A0W8000 L1A180W8000 L7A90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L1A180W8000 L7A90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L1A180W8000 180 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7A90W8000 90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL1A180W8000
+L1A180W8000 0 1.21634e-013
CL7A90W8000
+L7A90W8000 0 1.21634e-013
RLL1A0W8000_L1A180W8000 L1A0W8000 L1A180W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7A90W8000 L1A0W8000 L7A90W8000 1e-7 L=1.64454e-009
RLL1A180W8000_L7A90W8000 L1A180W8000 L7A90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L1A180W8000L7A90W8000_FST_6654
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000L7An90W8000_FST_218 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An225W8000L7An90W8000_FST_218
+L1A0W8000 L7An225W8000 L7An90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An225W8000 L7An90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An225W8000 -225 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
+ trace( L7An90W8000 -90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))