interconn.iml,1

于博士cadence视频配套工程文件

" ) 
   (Frequency 0 ) ) 
  (STL_1S_1R_9577 
   (IDL ".subckt STL_1S_1R_9577
+X1 0
+X2 0
*EMIinfo Type Top MicroStrip
*EMIinfo Conductor Width=12000 botDist=0.000508
*EMIinfo Dielectric Eps=4.5 Thick=0.000508
*EMIinfo Plane Z=0.00080264

.layerstack Layerstack3
+shield( 3.048e-005 1 0 )
+dielectric( 0.000508 4.5 0.035 )
.crosssection
+rectangle ( 5.959e+007 0 0.000508 0.0003048 0.00053848 )
+Length=length
.rlgc RLGCSTL_1S_1R_9577 ( Length=length N=1 )
.C 0
+ 6.811100e-011 
.L 0
+ 4.933300e-007 
.G 0
+ 0.000000e+000 
.R 0
+ 1.806300e+000 
.endrlgc RLGCSTL_1S_1R_9577

**The Characteristic Modal Delay, Admittance and
**Impedance Matrices of these Transmission Lines:

*Delay Matrix.
*Td 0 (n=1)
*  5.796700e-009 

*Admittance Matrix.
*Y 0 (n=1)
* 1.175000e-002 

*Impedance Matrix.
*Z 0 (n=1)
*  8.510600e+001 


**The Near-End Crosstalk Coefficent of these Transmission
**Lines based on Near-End Resistance=50 ohm assumption:

*Near-End Crosstalk Coefficent Matrix, Z0*Inv(R+Z0).
*  0 (n=1)
*  6.299200e-001 
.ends STL_1S_1R_9577
" ) 
   (KSPICE "DATAPOINTS RLGC STL_1S_1R_9577
FREQUENCY=0
CMATRIX
 6.811100e-011
LMATRIX
 4.933300e-007
GMATRIX
 0.000000e+000
RMATRIX
 1.806300e+000
END RLGC
" ) 
   (Frequency 0 ) ) 
  (STL_1S_1R_9579 
   (IDL ".subckt STL_1S_1R_9579
+X1 0
+X2 0
*EMIinfo Type Bottom MicroStrip
*EMIinfo Plane Z=0.00053848
*EMIinfo Dielectric Eps=4.5 Thick=0.000508
*EMIinfo Conductor Width=12000 topDist=0.000508

.layerstack Layerstack1
+dielectric( 0.000508 4.5 0.035 )
+shield( 3.048e-005 1 0 )
.crosssection
+rectangle ( 5.959e+007 0 -3.048e-005 0.0003048 0 )
+Length=length
.rlgc RLGCSTL_1S_1R_9579 ( Length=length N=1 )
.C 0
+ 6.811100e-011 
.L 0
+ 4.933300e-007 
.G 0
+ 0.000000e+000 
.R 0
+ 1.806300e+000 
.endrlgc RLGCSTL_1S_1R_9579

**The Characteristic Modal Delay, Admittance and
**Impedance Matrices of these Transmission Lines:

*Delay Matrix.
*Td 0 (n=1)
*  5.796700e-009 

*Admittance Matrix.
*Y 0 (n=1)
* 1.175000e-002 

*Impedance Matrix.
*Z 0 (n=1)
*  8.510600e+001 


**The Near-End Crosstalk Coefficent of these Transmission
**Lines based on Near-End Resistance=50 ohm assumption:

*Near-End Crosstalk Coefficent Matrix, Z0*Inv(R+Z0).
*  0 (n=1)
*  6.299200e-001 
.ends STL_1S_1R_9579
" ) 
   (KSPICE "DATAPOINTS RLGC STL_1S_1R_9579
FREQUENCY=0
CMATRIX
 6.811100e-011
LMATRIX
 4.933300e-007
GMATRIX
 0.000000e+000
RMATRIX
 1.806300e+000
END RLGC
" ) 
   (Frequency 0 ) ) ) 
 (Via 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_5309 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_5309
+L1A0W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.000812294 0.000812294) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.000812294 0.000812294) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1e-013
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_5309
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_713 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_713
+L1A0W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1e-013
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_713
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000_FST_7813 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000_FST_7813
+L1A0W8000 L7An180W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An180W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An180W8000 -180 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An180W8000
+L7An180W8000 0 1.82452e-013
RLL1A0W8000_L7An180W8000 L1A0W8000 L7An180W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000_FST_7813
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000_FST_7447 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000_FST_7447
+L1A0W8000 L7An90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An90W8000 -90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An90W8000
+L7An90W8000 0 1.82452e-013
RLL1A0W8000_L7An90W8000 L1A0W8000 L7An90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000_FST_7447
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000L7A0W8000_FST_7709 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000L7A0W8000_FST_7709
+L1A0W8000 L7An180W8000 L7A0W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An180W8000 L7A0W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An180W8000 -180 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
+ trace( L7A0W8000 0 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL7An180W8000
+L7An180W8000 0 1.21634e-013
CL7A0W8000
+L7A0W8000 0 1.21634e-013
RLL1A0W8000_L7An180W8000 L1A0W8000 L7An180W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7A0W8000 L1A0W8000 L7A0W8000 1e-7 L=1.64454e-009
RLL7An180W8000_L7A0W8000 L7An180W8000 L7A0W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000L7A0W8000_FST_7709
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_5377 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_5377
+L1A0W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1e-013
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000_FST_5377
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000_FST_4336 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000_FST_4336
+L1A0W8000 L7An180W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An180W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An180W8000 -180 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An180W8000
+L7An180W8000 0 1.82452e-013
RLL1A0W8000_L7An180W8000 L1A0W8000 L7An180W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000_FST_4336
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000_FST_4073 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000_FST_4073
+L1A0W8000 L7An90W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An90W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An90W8000 -90 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.82452e-013
CL7An90W8000
+L7An90W8000 0 1.82452e-013
RLL1A0W8000_L7An90W8000 L1A0W8000 L7An90W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An90W8000_FST_4073
" ) ) 
  (VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000L7A0W8000_FST_5788 
   (IDL "*There is a VIA here.
.subckt VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000L7A0W8000_FST_5788
+L1A0W8000 L7An180W8000 L7A0W8000 

.layerstack LayerStackAll
+dielectric( 4.5 0.00053848 )
+shield( SL5 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.0002032 )
+shield( SL3 5.959e+007 3.048e-005 )
+dielectric( 4.5 0.000508 )

.Via L1A0W8000 L7An180W8000 L7A0W8000 
+ pad( 0.00131064 0.00134112 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ void( 0.00077216 0.00080264 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ void( 0.00053848 0.00056896 ellipse(5.959e+007 0.0 0.0  0.0010064 0.0010064) )
+ pad( 0 3.048e-005 ellipse(5.959e+007 0.0 0.0  0.000599897 0.000599897))
+ drill(3.048e-005 0.00131064 ellipse(ml1 0.0 0.0 0.000350012 0.000350012))
+ trace( L1A0W8000 0 rectangle(5.959e+007 0.0 0.00131064 0.0002032 0.00134112))
+ trace( L7An180W8000 -180 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
+ trace( L7A0W8000 0 rectangle(5.959e+007 0.0 0 0.0002032 3.048e-005))
*FormulaModel via circuits
CL1A0W8000
+L1A0W8000 0 1.21634e-013
CL7An180W8000
+L7An180W8000 0 1.21634e-013
CL7A0W8000
+L7A0W8000 0 1.21634e-013
RLL1A0W8000_L7An180W8000 L1A0W8000 L7An180W8000 1e-7 L=1.64454e-009
RLL1A0W8000_L7A0W8000 L1A0W8000 L7A0W8000 1e-7 L=1.64454e-009
RLL7An180W8000_L7A0W8000 L7An180W8000 L7A0W8000 1e-7 L=1.64454e-009
.ends VIA_DSPSYSTEM_VIA60_35_95_L1A0W8000L7An180W8000L7A0W8000_FST_5788