myproj.vhd

于博士cadence视频配套工程文件

	\2\ => GND
);
C63 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C31 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C32 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C123 : \1uF\	PORT MAP(
	\1\ => N92855, 
	\2\ => ROUT
);
C96 : \1nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C64 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C155 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C97 : \1nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C156 : \10uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C124 : \1600pF\	PORT MAP(
	\1\ => N93069, 
	\2\ => GND
);
C33 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C65 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C34 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C98 : \1nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R70 : \33\	PORT MAP(
	\1\ => N81989, 
	\2\ => N91553
);
C66 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C125 : \2200pF\	PORT MAP(
	\1\ => N93029, 
	\2\ => GND
);
C99 : \1nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C67 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C35 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C126 : \2000pF\	PORT MAP(
	\1\ => N74096, 
	\2\ => GND
);
R71 : \3K\	PORT MAP(
	\1\ => CS_AOUT_LP, 
	\2\ => N61739
);
R72 : \12K\	PORT MAP(
	\1\ => N61739, 
	\2\ => N61747
);
C68 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C36 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R40 : \1K\	PORT MAP(
	\1\ => DSP_HD14, 
	\2\ => GND
);
C127 : \2200pF\	PORT MAP(
	\1\ => N74104, 
	\2\ => GND
);
C69 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C37 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C128 : \220pF\	PORT MAP(
	\1\ => GND, 
	\2\ => N73720
);
R41 : \10K\	PORT MAP(
	\1\ => DSP_HD12, 
	\2\ => VCC3V3
);
R73 : \3K\	PORT MAP(
	\1\ => N61747, 
	\2\ => N66431
);
R74 : \15K\	PORT MAP(
	\1\ => N61747, 
	\2\ => GND
);
C38 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C129 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VP
);
R42 : \1K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => N1515580
);
R10 : \33\	PORT MAP(
	\1\ => N1021779, 
	\2\ => N1028649
);
R43 : \10K\	PORT MAP(
	\1\ => DSP_HD8, 
	\2\ => VCC3V3
);
R11 : \33\	PORT MAP(
	\1\ => REF4_OUT, 
	\2\ => DSP_CLKIN
);
C39 : \1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R75 : \15K\	PORT MAP(
	\1\ => N73672, 
	\2\ => N73692
);
R76 : \15K\	PORT MAP(
	\1\ => N93029, 
	\2\ => N92903
);
R44 : \1K\	PORT MAP(
	\1\ => DSP_HD4, 
	\2\ => VCC3V3
);
R12 : \33\	PORT MAP(
	\1\ => REF2_OUT, 
	\2\ => MCBSP_CLKIN
);
R45 : \1K\	PORT MAP(
	\1\ => DSP_HD3, 
	\2\ => GND
);
R77 : \3K\	PORT MAP(
	\1\ => CS_AOUT_RN, 
	\2\ => N73984
);
R13 : \33\	PORT MAP(
	\1\ => N1166110, 
	\2\ => CS4272_SCLK
);
J1 : CON4	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => VCC12VN, 
	\3\ => GND, 
	\4\ => VCC5V
);
R46 : \10K\	PORT MAP(
	\1\ => CE0, 
	\2\ => VCC3V3
);
R78 : \12K\	PORT MAP(
	\1\ => N73984, 
	\2\ => N73672
);
R14 : \33\	PORT MAP(
	\1\ => N1166296, 
	\2\ => CS4272_LRCLK
);
R15 : \33\	PORT MAP(
	\1\ => N1166483, 
	\2\ => CS4272_SDIN
);
R79 : \3K\	PORT MAP(
	\1\ => N73672, 
	\2\ => N73648
);
R47 : \10K\	PORT MAP(
	\1\ => DSP_EMU0, 
	\2\ => VCC3V3
);
J2 : \HEADER 7X2\	PORT MAP(
	\2\ => GND, 
	\4\ => GND, 
	\6\ => GND, 
	\8\ => GND, 
	\10\ => GND, 
	\12\ => GND, 
	\14\ => GND, 
	\1\ => CLKX1, 
	\3\ => FSX1, 
	\5\ => DX1, 
	\7\ => CLKR1, 
	\9\ => FSR1, 
	\11\ => DR1_SDA1, 
	\13\ => CLKS1_SCL1
);
R16 : \0\	PORT MAP(
	\1\ => SCL_M0, 
	\2\ => SCL0
);
J3 : JTAG	PORT MAP(
	TMS => DSP_TMS, 
	TDI => DSP_TDI, 
	PD_VCC => VCC3V3, 
	TDO => DSP_TDO, 
	TCK_RET => DSP_TCK, 
	TCK => DSP_TCK, 
	EMU0 => DSP_EMU0, 
	EMU1 => DSP_EMU1, 
	GND_12 => GND, 
	GND_10 => GND, 
	GND_8 => GND, 
	GND_4 => GND, 
	\T\\R\\S\\T\\\ => \DSP_TRST#\, 
	NC => OPEN
);
R48 : \10K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => DSP_EMU1
);
R49 : \10K\	PORT MAP(
	\1\ => CE1, 
	\2\ => VCC3V3
);
J4 : \HEADER 5X2\	PORT MAP(
	\2\ => GP_INT4, 
	\4\ => GP_INT5, 
	\6\ => GP_INT6, 
	\8\ => GP_INT7, 
	\10\ => NMI, 
	\1\ => GND, 
	\3\ => GND, 
	\5\ => GND, 
	\7\ => GND, 
	\9\ => GND
);
R17 : \0\	PORT MAP(
	\1\ => SDA_M1, 
	\2\ => SDA0
);
D1 : LED	PORT MAP(
	ANODE => VCC3V3, 
	CATHODE => N1515374
);
J5 : \HEADER 6X2\	PORT MAP(
	\2\ => CLKOUT2, 
	\4\ => CLKOUT3, 
	\6\ => TOUT0, 
	\8\ => TINP0, 
	\10\ => TOUT1, 
	\12\ => TINP1, 
	\1\ => GND, 
	\3\ => GND, 
	\5\ => GND, 
	\7\ => GND, 
	\9\ => GND, 
	\11\ => GND
);
R18 : \10K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => SCL0
);
D2 : LED	PORT MAP(
	ANODE => N1515548, 
	CATHODE => N1515650
);
J6 : AUDIO_RJ	PORT MAP(
	GND => GND, 
	R => ROUT, 
	L => LOUT, 
	NCR => OPEN, 
	NCL => OPEN
);
R19 : \10K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => SDA0
);
J7 : AUDIO_RJ	PORT MAP(
	GND => GND, 
	R => RIN, 
	L => LIN, 
	NCR => OPEN, 
	NCL => OPEN
);
D3 : LED	PORT MAP(
	ANODE => VCC3V3, 
	CATHODE => N1515378
);
SW1 : \DSP-RESET\	PORT MAP(
	\1\ => GND, 
	\3\ => N1515650, 
	\2\ => GND, 
	\4\ => N1515650
);
C70 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C130 : \10uF\	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => GND
);
C71 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C131 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C40 : \10uF\	PORT MAP(
	\1\ => DSP_PLLHV, 
	\2\ => GND
);
C72 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C100 : \1nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C132 : \10uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C73 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C41 : \0.1uF\	PORT MAP(
	\1\ => DSP_PLLHV, 
	\2\ => GND
);
C133 : \470pF\	PORT MAP(
	\1\ => N44356, 
	\2\ => N43972
);
C101 : \220pF\	PORT MAP(
	\1\ => N52333, 
	\2\ => N52922
);
C42 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C74 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C10 : \0.1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C102 : \220pF\	PORT MAP(
	\1\ => N77030, 
	\2\ => N81989
);
C75 : \2.2uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C43 : \2.2uF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C11 : \1uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C134 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VP
);
C76 : \2.2uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C135 : \10uF\	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => GND
);
C12 : \0.1uF\	PORT MAP(
	\1\ => N261524, 
	\2\ => GND
);
R80 : \10K\	PORT MAP(
	\1\ => N73916, 
	\2\ => N73968
);
C103 : \2000pF\	PORT MAP(
	\1\ => N47737, 
	\2\ => GND
);
C44 : \2.2uF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C45 : \2.2uF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C13 : \1uF\	PORT MAP(
	\1\ => N261524, 
	\2\ => GND
);
C77 : \2.2uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R81 : \4.7K\	PORT MAP(
	\1\ => N73692, 
	\2\ => N73916
);
C104 : \2200pF\	PORT MAP(
	\1\ => N48145, 
	\2\ => GND
);
C136 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C105 : \1uF\	PORT MAP(
	\1\ => N91553, 
	\2\ => LOUT
);
C137 : \10uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C78 : \2.2uF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R50 : \10K\	PORT MAP(
	\1\ => CE2, 
	\2\ => VCC3V3
);
C14 : \20uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
R82 : \3K\	PORT MAP(
	\1\ => N73968, 
	\2\ => N93069
);
C46 : \2.2uF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C79 : \100nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R51 : \10K\	PORT MAP(
	\1\ => CE3, 
	\2\ => VCC3V3
);
C106 : \1600pF\	PORT MAP(
	\1\ => N75565, 
	\2\ => GND
);
C47 : \220nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C15 : \0.1uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
R83 : \12K\	PORT MAP(
	\1\ => N93069, 
	\2\ => N93029
);
C138 : \470pF\	PORT MAP(
	\1\ => N10740, 
	\2\ => N10780
);
R52 : \10K\	PORT MAP(
	\1\ => ARE, 
	\2\ => VCC3V3
);
C139 : \1uF\	PORT MAP(
	\1\ => N44344, 
	\2\ => RIN
);
C48 : \220nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C107 : \2200pF\	PORT MAP(
	\1\ => N75509, 
	\2\ => GND
);
R84 : \3K\	PORT MAP(
	\1\ => N93029, 
	\2\ => N92923
);
C16 : \20uF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
R20 : \10K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => DR1_SDA1
);
R53 : \10K\	PORT MAP(
	\1\ => AOE, 
	\2\ => VCC3V3
);
C49 : \220nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C17 : \10uF\	PORT MAP(
	\1\ => N1041204, 
	\2\ => GND
);
C108 : \2000pF\	PORT MAP(
	\1\ => N61739, 
	\2\ => GND
);
R85 : \33\	PORT MAP(
	\1\ => N92903, 
	\2\ => N92855
);
R21 : \10K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => CLKS1_SCL1
);
R22 : RS4	PORT MAP(
	\1\ => ED0, 
	\2\ => ED1, 
	\3\ => ED2, 
	\4\ => ED3, 
	\5\ => R_ED3, 
	\6\ => R_ED2, 
	\7\ => R_ED1, 
	\8\ => R_ED0
);
R86 : \3K\	PORT MAP(
	\1\ => CS_AOUT_RP, 
	\2\ => N74096
);
N1 : NE5532	PORT MAP(
	\AIN-\ => N52333, 
	\AIN+\ => N66431, 
	AOUT => N52922, 
	VCC => VCC12VP, 
	GND => VCC12VN, 
	\BIN+\ => GND, 
	\BIN-\ => N59644, 
	BOUT => N60492
);
C18 : \1uF\	PORT MAP(
	\1\ => N1022674, 
	\2\ => GND
);
C109 : \2200pF\	PORT MAP(
	\1\ => N61747, 
	\2\ => GND
);
R54 : \10K\	PORT MAP(
	\1\ => AWE, 
	\2\ => VCC3V3
);
C19 : \1uF\	PORT MAP(
	\1\ => N1026167, 
	\2\ => GND
);
R23 : RS4	PORT MAP(
	\1\ => EA2, 
	\2\ => EA3, 
	\3\ => EA4, 
	\4\ => EA5, 
	\5\ => R_EA5, 
	\6\ => R_EA4, 
	\7\ => R_EA3, 
	\8\ => R_EA2
);
N2 : NE5532	PORT MAP(
	\AIN-\ => N77030, 
	\AIN+\ => GND, 
	AOUT => N81989, 
	VCC => VCC12VP, 
	GND => VCC12VN, 
	\BIN+\ => GND, 
	\BIN-\ => N92923, 
	BOUT => N92903
);
R87 : \12K\	PORT MAP(
	\1\ => N74096, 
	\2\ => N74104
);
R55 : \10K\	PORT MAP(
	\1\ => BUSRQ, 
	\2\ => VCC3V3
);
R24 : RS4	PORT MAP(
	\1\ => ED4, 
	\2\ => ED5, 
	\3\ => ED6, 
	\4\ => ED7, 
	\5\ => R_ED7, 
	\6\ => R_ED6, 
	\7\ => R_ED5, 
	\8\ => R_ED4
);
R88 : \3K\	PORT MAP(
	\1\ => N74104, 
	\2\ => N73720
);
R56 : \10K\	PORT MAP(
	\1\ => HOLD, 
	\2\ => VCC3V3
);
N3 : NE5532	PORT MAP(
	\AIN-\ => N73648, 
	\AIN+\ => N73720, 
	AOUT => N73692, 
	VCC => VCC12VP, 
	GND => VCC12VN, 
	\BIN+\ => GND, 
	\BIN-\ => N73916, 
	BOUT => N73968
);
END STRUCTURE;