📄 myproj.vhd
字号:
\2\ => ED21,
\3\ => ED22,
\4\ => ED23,
\5\ => R_ED23,
\6\ => R_ED22,
\7\ => R_ED21,
\8\ => R_ED20
);
C119 : \220pF\ PORT MAP(
\1\ => N73648,
\2\ => N73692
);
U5 : CY2303 PORT MAP(
REF => REF_OUT,
GND => GND,
REFIN => N1028649,
NC => OPEN,
REF2 => REF2_OUT,
REF4 => REF4_OUT,
VDD => N1026167,
OE => VCC3V3
);
R3 : \10K\ PORT MAP(
\1\ => SCL_M0,
\2\ => VCC3V3
);
C29 : \47uF\ PORT MAP(
\1\ => GND,
\2\ => VCC12VN
);
R4 : \10K\ PORT MAP(
\1\ => SCL_M0,
\2\ => GND
);
U6 : TMS320C6713GDP PORT MAP(
ED0 => ED0,
ED1 => ED1,
ED2 => ED2,
ED3 => ED3,
ED4 => ED4,
ED5 => ED5,
ED6 => ED6,
ED7 => ED7,
ED8 => ED8,
ED9 => ED9,
ED10 => ED10,
ED11 => ED11,
ED12 => ED12,
ED13 => ED13,
ED14 => ED14,
ED15 => ED15,
EA2 => EA2,
EA3 => EA3,
EA4 => EA4,
EA5 => EA5,
EA6 => EA6,
EA7 => EA7,
EA8 => EA8,
EA9 => EA9,
EA10 => EA10,
EA11 => EA11,
EA12 => EA12,
EA13 => EA13,
EA14 => EA14,
EA15 => EA15,
EA16 => EA16,
EA17 => EA17,
EA18 => EA18,
EA19 => EA19,
EA20 => EA20,
EA21 => OPEN,
\C\\E\\0\\\ => CE0,
\C\\E\\1\\\ => CE1,
\C\\E\\2\\\ => CE2,
\C\\E\\3\\\ => CE3,
\B\\E\\0\\\ => BE0,
\B\\E\\1\\\ => BE1,
\H\\O\\L\\D\\A\\\ => HOLDA,
\H\\O\\L\\D\\\ => HOLD,
BUSREQ => BUSRQ,
ECLKIN => 'Z',
ECLKOUT => ECLKOUT,
\AR\\E\\/SD\\C\\A\\S\\/SS\\A\\D\\S\\\ => ARE,
\AO\\E\\/SD\\R\\A\\S\\/SS\\O\\E\\\ => AOE,
\AW\\E\\/SD\\W\\E\\/SS\\W\\E\\\ => AWE,
ARDY => ARDY,
ED16 => ED16,
ED17 => ED17,
ED18 => ED18,
ED19 => ED19,
ED20 => ED20,
ED21 => ED21,
ED22 => ED22,
ED23 => ED23,
ED24 => ED24,
ED25 => ED25,
ED26 => ED26,
ED27 => ED27,
ED28 => ED28,
ED29 => ED29,
ED30 => ED30,
ED31 => ED31,
\B\\E\\2\\\ => BE2,
\B\\E\\3\\\ => BE3,
\HD15/GP[15]\ => DSP_GP15,
\HD14/GP[14]\ => DSP_HD14,
\HD13/GP[13]\ => DSP_GP13,
\HD7/GP[3]\ => OPEN,
\HD3/AMUTE1\ => DSP_HD3,
\H\\I\\N\\T\\/GP[1]\ => OPEN,
\HD4/GP[0]\ => DSP_HD4,
\HD12/GP[12]\ => DSP_HD12,
\HD11/GP[11]\ => OPEN,
\HD10/GP[10]\ => CS4272_RESET,
\HD9/GP[9]\ => OPEN,
\HD8/GP[8]\ => DSP_HD8,
\HD6/AHCKR1\ => OPEN,
\HD5/AHCKX1\ => OPEN,
\HD1/AXR1[7]\ => OPEN,
\HD2/AFSX1\ => OPEN,
\HD0/AXR1[4]\ => OPEN,
\HCNTL1/AXR1[1]\ => 'Z',
\HCNTL0/AXR1[3]\ => 'Z',
\HHWIL/AFSR1\ => 'Z',
\HR/W\\/AXR1[0]\ => 'Z',
\H\\A\\S\\/ACLKX1\ => 'Z',
\H\\R\\D\\Y\\/ACLKR1\ => OPEN,
\H\\D\\S\\2\\/AXR1[5]\ => 'Z',
\H\\D\\S\\1\\/AXR1[6]\ => 'Z',
\HCS/AXR1[2]\ => 'Z',
\R\\E\\S\\E\\T\\\ => N1515650,
NMI => NMI,
\GP[7]/(EXT_INT7)\ => GP_INT7,
\GP[6]/(EXT_INT6)\ => GP_INT6,
\GP[5]/(EXT_INT5)/AMUTEIN0\ => GP_INT5,
\GP[4]/(EXT_INT4)/AMUTEIN1\ => GP_INT4,
\TOUT1/AXR0[4]\ => TOUT1,
\TINP1/AHCLKX0\ => TINP1,
\TOUT0/AXR0[2]\ => TOUT0,
\TINP0/AXR0[3]\ => TINP0,
CLKIN => DSP_CLKIN,
\CLOKOUT2/GP[2]\ => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKMODE0 => N1515580,
PLLHV => DSP_PLLHV,
TMS => DSP_TMS,
TDO => DSP_TDO,
TDI => DSP_TDI,
TCK => DSP_TCK,
\T\\R\\S\\T\\\ => \DSP_TRST#\,
EMU1 => DSP_EMU1,
EMU0 => DSP_EMU0,
EMU2 => OPEN,
EMU3 => OPEN,
EMU4 => OPEN,
EMU5 => OPEN,
\CLKX1/AMUTE0\ => CLKX1,
FSX1 => FSX1,
\DX1/AXR0[5]\ => DX1,
\CLKR1/AXR0[6]\ => CLKR1,
\FSR1/AXR0[7]\ => FSR1,
\DR1/SDA1\ => DR1_SDA1,
\CLKS1/SCL1\ => CLKS1_SCL1,
\CLKX0/ACLKX0\ => N1166110,
\FSX0/AFSX0\ => N1166296,
\DX0/AXR0[1]\ => N1166483,
\CLKR0/ACLKR0\ => CS4272_SCLK,
\FSR0/AFSR0\ => CS4272_LRCLK,
\DR0/AXR0[0]\ => CS4272_SDOUT,
\CLKS0/AHCLKR0\ => MCBSP_CLKIN,
SCL0 => SCL0,
SDA0 => SDA0,
DVDD1 => VCC3V3,
DVDD2 => VCC3V3,
DVDD3 => VCC3V3,
DVDD4 => VCC3V3,
DVDD5 => VCC3V3,
DVDD6 => VCC3V3,
DVDD7 => VCC3V3,
DVDD8 => VCC3V3,
DVDD9 => VCC3V3,
DVDD10 => VCC3V3,
DVDD12 => VCC3V3,
DVDD13 => VCC3V3,
DVDD14 => VCC3V3,
DVDD15 => VCC3V3,
DVDD16 => VCC3V3,
DVDD17 => VCC3V3,
DVDD18 => VCC3V3,
DVDD19 => VCC3V3,
DVDD20 => VCC3V3,
DVDD11 => VCC3V3,
RSV1 => OPEN,
RSV2 => OPEN,
RSV3 => OPEN,
RSV4 => N2240979,
RSV5 => VCC1V2,
RSV6 => GND,
CVDD_32 => VCC1V2,
CVDD_31 => VCC1V2,
CVDD_30 => VCC1V2,
CVDD_29 => VCC1V2,
CVDD_28 => VCC1V2,
CVDD_27 => VCC1V2,
CVDD_26 => VCC1V2,
CVDD_25 => VCC1V2,
CVDD_24 => VCC1V2,
CVDD_23 => VCC1V2,
CVDD_22 => VCC1V2,
CVDD_21 => VCC1V2,
CVDD_20 => VCC1V2,
CVDD_19 => VCC1V2,
CVDD_18 => VCC1V2,
CVDD_17 => VCC1V2,
CVDD_16 => VCC1V2,
CVDD_15 => VCC1V2,
CVDD_14 => VCC1V2,
CVDD_13 => VCC1V2,
CVDD_12 => VCC1V2,
CVDD_11 => VCC1V2,
CVDD_10 => VCC1V2,
CVDD_9 => VCC1V2,
CVDD_8 => VCC1V2,
CVDD_7 => VCC1V2,
CVDD_6 => VCC1V2,
CVDD_5 => VCC1V2,
CVDD_4 => VCC1V2,
CVDD_3 => VCC1V2,
CVDD_2 => VCC1V2,
CVDD_1 => VCC1V2,
DVDD21 => VCC3V3,
DVDD22 => VCC3V3,
DVDD23 => VCC3V3,
DVDD24 => VCC3V3,
DVDD25 => VCC3V3,
DVDD26 => VCC3V3,
DVDD27 => VCC3V3,
RSV7 => OPEN,
VSS0 => GND,
VSS1 => GND,
VSS2 => GND,
VSS3 => GND,
VSS4 => GND,
VSS5 => GND,
VSS6 => GND,
VSS7 => GND,
VSS8 => GND,
VSS9 => GND,
VSS10 => GND,
VSS11 => GND,
VSS12 => GND,
VSS13 => GND,
VSS14 => GND,
VSS15 => GND,
VSS16 => GND,
VSS17 => GND,
VSS18 => GND,
VSS19 => GND,
VSS20 => GND,
VSS21 => GND,
VSS22 => GND,
VSS23 => GND,
VSS24 => GND,
VSS25 => GND,
VSS26 => GND,
VSS27 => GND,
VSS28 => GND,
VSS29 => GND,
VSS30 => GND,
VSS31 => GND,
VSS32 => GND,
VSS33 => GND,
VSS34 => GND,
VSS35 => GND,
VSS36 => GND,
VSS37 => GND,
VSS38 => GND,
VSS39 => GND,
VSS40 => GND,
VSS41 => GND,
VSS42 => GND,
VSS43 => GND,
VSS44 => GND,
VSS45 => GND,
VSS46 => GND,
VSS47 => GND,
VSS48 => GND,
VSS49 => GND,
VSS50 => GND,
VSS51 => GND,
VSS52 => GND,
VSS53 => GND,
VSS54 => GND,
VSS55 => GND,
VSS56 => GND,
VSS57 => GND,
VSS58 => GND,
VSS59 => GND,
VSS60 => GND,
VSS61 => GND,
VSS62 => GND,
VSS63 => GND,
VSS64 => GND,
VSS65 => GND,
VSS66 => GND,
VSS67 => GND,
VSS68 => GND
);
R65 : \10K\ PORT MAP(
\1\ => N59644,
\2\ => N60492
);
R33 : RS4 PORT MAP(
\1\ => EA18,
\2\ => EA19,
\3\ => EA20,
\4\ => OPEN,
\5\ => OPEN,
\6\ => R_EA20,
\7\ => R_EA19,
\8\ => R_EA18
);
R97 : \634\ PORT MAP(
\1\ => N43972,
\2\ => N44000
);
R5 : \10K\ PORT MAP(
\1\ => SDA_M1,
\2\ => GND
);
R66 : \4.7K\ PORT MAP(
\1\ => N52922,
\2\ => N59644
);
R34 : RS4 PORT MAP(
\1\ => ED24,
\2\ => ED25,
\3\ => ED26,
\4\ => ED27,
\5\ => R_ED27,
\6\ => R_ED26,
\7\ => R_ED25,
\8\ => R_ED24
);
L1 : FB PORT MAP(
\1\ => N256686,
\2\ => VCC5V
);
R98 : \100K\ PORT MAP(
\1\ => N10593,
\2\ => N11845
);
U7 : \MT48LC2M32B2B5-6\ PORT MAP(
DQ0 => R_ED0,
DQ1 => R_ED1,
DQ2 => R_ED2,
DQ3 => R_ED3,
DQ4 => R_ED4,
DQ5 => R_ED5,
DQ6 => R_ED6,
DQ7 => R_ED7,
DQ8 => R_ED8,
DQ9 => R_ED9,
DQ10 => R_ED10,
DQ11 => R_ED11,
DQ12 => R_ED12,
DQ13 => R_ED13,
DQ14 => R_ED14,
DQ15 => R_ED15,
DQ16 => R_ED16,
DQ17 => R_ED17,
DQ18 => R_ED18,
DQ19 => R_ED19,
DQ20 => R_ED20,
DQ21 => R_ED21,
DQ22 => R_ED22,
DQ23 => R_ED23,
DQ24 => R_ED24,
DQ25 => R_ED25,
DQ26 => R_ED26,
DQ27 => R_ED27,
DQ28 => R_ED28,
DQ29 => R_ED29,
DQ30 => R_ED30,
DQ31 => R_ED31,
A0 => R_EA2,
A1 => R_EA3,
A2 => R_EA4,
A3 => R_EA5,
A4 => R_EA6,
A5 => R_EA7,
A6 => R_EA8,
A7 => R_EA9,
A8 => R_EA10,
A9 => R_EA11,
A10 => R_EA12,
BA0 => R_EA13,
BA1 => R_EA14,
DQM0 => BE0,
DQM1 => BE1,
DQM2 => BE2,
DQM3 => BE3,
CLK => R_ECLKOUT,
CKE => CKE,
\CS#\ => CE0,
\WE#\ => R_AWE,
\CAS#\ => R_ARE,
\RAS#\ => R_AOE,
VDDQ0 => VCC3V3,
VDDQ1 => VCC3V3,
VDDQ2 => VCC3V3,
VDDQ3 => VCC3V3,
VDDQ4 => VCC3V3,
VDDQ5 => VCC3V3,
VDDQ6 => VCC3V3,
VDDQ7 => VCC3V3,
VSSQ0 => GND,
VSSQ1 => GND,
VSSQ2 => GND,
VSSQ3 => GND,
VSSQ4 => GND,
VSSQ5 => GND,
VSSQ6 => GND,
VSSQ7 => GND,
VDD_1 => VCC3V3,
VDD_15 => VCC3V3,
VDD_29 => VCC3V3,
VDD_43 => VCC3V3,
VSS_44 => GND,
VSS_58 => GND,
VSS_72 => GND,
VSS_86 => GND,
NC0 => 'Z',
NC1 => 'Z',
NC2 => 'Z',
NC3 => 'Z',
NC4 => 'Z',
NC5 => 'Z',
NC6 => 'Z'
);
R67 : \3K\ PORT MAP(
\1\ => N60492,
\2\ => N75565
);
R6 : \10K\ PORT MAP(
\1\ => SDA_M1,
\2\ => VCC3V3
);
L2 : FB PORT MAP(
\1\ => VCC5V,
\2\ => N1022674
);
R99 : \634\ PORT MAP(
\1\ => N44000,
\2\ => CS_AIN_RN
);
U8 : SST39VF800A PORT MAP(
A1 => R_EA3,
A2 => R_EA4,
A3 => R_EA5,
A4 => R_EA6,
A5 => R_EA7,
A6 => R_EA8,
A7 => R_EA9,
A8 => R_EA10,
A9 => R_EA11,
A10 => R_EA12,
A11 => R_EA13,
A12 => R_EA14,
A13 => R_EA15,
A14 => R_EA16,
A15 => R_EA17,
A16 => R_EA18,
A17 => R_EA19,
A18 => R_EA20,
DQ0 => R_ED0,
DQ1 => R_ED1,
DQ2 => R_ED2,
DQ3 => R_ED3,
DQ4 => R_ED4,
DQ5 => R_ED5,
DQ6 => R_ED6,
DQ7 => R_ED7,
DQ8 => R_ED8,
DQ9 => R_ED9,
DQ10 => R_ED10,
DQ11 => R_ED11,
DQ12 => R_ED12,
DQ13 => R_ED13,
DQ14 => R_ED14,
DQ15 => R_ED15,
A0 => R_EA2,
\CE#\ => CE1,
\OE#\ => R_AOE,
\WE#\ => R_AWE,
VDD => VCC3V3,
VSS_27 => GND,
VSS_46 => GND,
NC1 => OPEN,
NC2 => OPEN,
NC7 => OPEN,
NC3 => OPEN,
NC4 => OPEN,
NC5 => OPEN,
NC6 => OPEN
);
R35 : RS4 PORT MAP(
\1\ => ARE,
\2\ => AOE,
\3\ => AWE,
\4\ => ECLKOUT,
\5\ => R_ECLKOUT,
\6\ => R_AWE,
\7\ => R_AOE,
\8\ => R_ARE
);
R7 : \1K\ PORT MAP(
\1\ => VCC1V2,
\2\ => N1041204
);
R36 : RS4 PORT MAP(
\1\ => ED28,
\2\ => ED29,
\3\ => ED30,
\4\ => ED31,
\5\ => R_ED31,
\6\ => R_ED30,
\7\ => R_ED29,
\8\ => R_ED28
);
R68 : \12K\ PORT MAP(
\1\ => N75565,
\2\ => N75509
);
L3 : FB PORT MAP(
\1\ => VCC3V3,
\2\ => N1026167
);
R37 : \1K\ PORT MAP(
\1\ => DSP_GP15,
\2\ => N1515374
);
L4 : FB PORT MAP(
\1\ => VCC3V3,
\2\ => DSP_PLL_FB
);
R8 : \0\ PORT MAP(
\1\ => N1041204,
\2\ => GND
);
R69 : \3K\ PORT MAP(
\1\ => N75509,
\2\ => N77030
);
R38 : \1K\ PORT MAP(
\1\ => N1515548,
\2\ => VCC3V3
);
R9 : \33\ PORT MAP(
\1\ => REF_OUT,
\2\ => CS4272_MCLK
);
R39 : \1K\ PORT MAP(
\1\ => DSP_GP13,
\2\ => N1515378
);
C1 : \0.1uF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C2 : \1uF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C3 : \0.1uF\ PORT MAP(
\1\ => N257675,
\2\ => GND
);
C4 : \20uF\ PORT MAP(
\1\ => VCC5V,
\2\ => GND
);
C5 : \10uF\ PORT MAP(
\1\ => N257675,
\2\ => GND
);
C6 : \1uF\ PORT MAP(
\1\ => VCC5V,
\2\ => GND
);
C7 : \20uF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C8 : \0.1uF\ PORT MAP(
\1\ => N256686,
\2\ => GND
);
C9 : \1uF\ PORT MAP(
\1\ => N256686,
\2\ => GND
);
C90 : \1nF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C91 : \1nF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C150 : \0.1uF\ PORT MAP(
\1\ => VCC5V,
\2\ => GND
);
C92 : \1nF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C151 : \0.01uF\ PORT MAP(
\1\ => GND,
\2\ => N43948
);
C60 : \2.2nF\ PORT MAP(
\1\ => VCC1V2,
\2\ => GND
);
C61 : \2.2nF\ PORT MAP(
\1\ => VCC1V2,
\2\ => GND
);
C152 : \100uF\ PORT MAP(
\1\ => N43948,
\2\ => GND
);
C93 : \1nF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C120 : \220pF\ PORT MAP(
\1\ => N92923,
\2\ => N92903
);
C62 : \2.2nF\ PORT MAP(
\1\ => VCC1V2,
\2\ => GND
);
C153 : \0.1uF\ PORT MAP(
\1\ => GND,
\2\ => VCC12VP
);
C30 : \0.1uF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C94 : \1nF\ PORT MAP(
\1\ => VCC3V3,
\2\ => GND
);
C121 : \2000pF\ PORT MAP(
\1\ => N73984,
\2\ => GND
);
C154 : \10uF\ PORT MAP(
\1\ => VCC12VP,
\2\ => GND
);
C122 : \2200pF\ PORT MAP(
\1\ => N73672,
\2\ => GND
);
C95 : \1nF\ PORT MAP(
\1\ => VCC3V3,
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