myproj.vhd

于博士cadence视频配套工程文件

SIGNAL N73648 : std_logic;
SIGNAL N77030 : std_logic;
SIGNAL N92903 : std_logic;
SIGNAL N93069 : std_logic;
SIGNAL N44344 : std_logic;
SIGNAL N48145 : std_logic;
SIGNAL N74104 : std_logic;
SIGNAL N47737 : std_logic;
SIGNAL N11209 : std_logic;
SIGNAL ROUT : std_logic;
SIGNAL N75565 : std_logic;
SIGNAL N10740 : std_logic;
SIGNAL N74096 : std_logic;
SIGNAL N92855 : std_logic;
SIGNAL N10593 : std_logic;
SIGNAL N61747 : std_logic;
SIGNAL N73720 : std_logic;
SIGNAL N44356 : std_logic;
SIGNAL N52333 : std_logic;
SIGNAL N2240979 : std_logic;
SIGNAL R_EA12 : std_logic;
SIGNAL R_EA18 : std_logic;
SIGNAL R_ED7 : std_logic;
SIGNAL AOE : std_logic;
SIGNAL EA11 : std_logic;
SIGNAL CE2 : std_logic;
SIGNAL ARE : std_logic;
SIGNAL ED22 : std_logic;
SIGNAL R_ED22 : std_logic;
SIGNAL DSP_HD3 : std_logic;
SIGNAL DSP_TDI : std_logic;
SIGNAL EA18 : std_logic;
SIGNAL R_EA11 : std_logic;
SIGNAL R_EA19 : std_logic;
SIGNAL R_ED19 : std_logic;
SIGNAL EA10 : std_logic;
SIGNAL TINP1 : std_logic;
SIGNAL ED14 : std_logic;
SIGNAL EA20 : std_logic;
SIGNAL CLKOUT3 : std_logic;
SIGNAL R_ED21 : std_logic;
SIGNAL R_EA10 : std_logic;
SIGNAL EA17 : std_logic;
SIGNAL R_ED18 : std_logic;
SIGNAL ED7 : std_logic;
SIGNAL TOUT1 : std_logic;
SIGNAL EA19 : std_logic;
SIGNAL CE3 : std_logic;
SIGNAL ED13 : std_logic;
SIGNAL EA9 : std_logic;
SIGNAL R_EA9 : std_logic;
SIGNAL R_ED17 : std_logic;
SIGNAL BE0 : std_logic;
SIGNAL ED6 : std_logic;
SIGNAL TINP0 : std_logic;
SIGNAL DSP_TMS : std_logic;
SIGNAL DSP_HD4 : std_logic;
SIGNAL R_ED20 : std_logic;
SIGNAL ED25 : std_logic;
SIGNAL R_EA8 : std_logic;
SIGNAL EA2 : std_logic;
SIGNAL R_EA20 : std_logic;
SIGNAL BE1 : std_logic;
SIGNAL ED5 : std_logic;
SIGNAL R_ED6 : std_logic;
SIGNAL TOUT0 : std_logic;
SIGNAL R_EA3 : std_logic;
SIGNAL CE1 : std_logic;
SIGNAL R_EA7 : std_logic;
SIGNAL DSP_PLL_FB : std_logic;
SIGNAL ED24 : std_logic;
SIGNAL BE2 : std_logic;
SIGNAL ED4 : std_logic;
SIGNAL R_ED5 : std_logic;
SIGNAL R_AOE : std_logic;
SIGNAL R_ED16 : std_logic;
SIGNAL DSP_EMU0 : std_logic;
SIGNAL ED23 : std_logic;
SIGNAL R_EA2 : std_logic;
SIGNAL BE3 : std_logic;
SIGNAL ED3 : std_logic;
SIGNAL R_ED4 : std_logic;
SIGNAL R_ED8 : std_logic;
SIGNAL ED31 : std_logic;
SIGNAL R_ED15 : std_logic;
SIGNAL R_ED31 : std_logic;
SIGNAL R_ED9 : std_logic;
SIGNAL CE0 : std_logic;
SIGNAL ED21 : std_logic;
SIGNAL R_ED14 : std_logic;
SIGNAL ED30 : std_logic;
SIGNAL R_EA17 : std_logic;
SIGNAL R_ED30 : std_logic;
SIGNAL R_ED10 : std_logic;
SIGNAL R_ED3 : std_logic;
SIGNAL ED2 : std_logic;
SIGNAL DSP_HD14 : std_logic;
SIGNAL R_ED13 : std_logic;
SIGNAL ED29 : std_logic;
SIGNAL N1515378 : std_logic;
SIGNAL ED1 : std_logic;
SIGNAL R_ED29 : std_logic;
SIGNAL R_ED11 : std_logic;
SIGNAL R_ED2 : std_logic;
SIGNAL GP_INT4 : std_logic;
SIGNAL R_EA16 : std_logic;
SIGNAL DSP_HD12 : std_logic;
SIGNAL ED28 : std_logic;
SIGNAL R_ED26 : std_logic;
SIGNAL HOLD : std_logic;
SIGNAL AWE : std_logic;
SIGNAL R_ED12 : std_logic;
SIGNAL R_ED28 : std_logic;
SIGNAL R_EA13 : std_logic;
SIGNAL ED20 : std_logic;
SIGNAL R_ED1 : std_logic;
SIGNAL ED27 : std_logic;
SIGNAL R_EA15 : std_logic;
SIGNAL R_ED0 : std_logic;
SIGNAL BUSRQ : std_logic;
SIGNAL DSP_EMU1 : std_logic;
SIGNAL R_ED25 : std_logic;
SIGNAL R_ED27 : std_logic;
SIGNAL R_EA14 : std_logic;
SIGNAL N1515580 : std_logic;
SIGNAL ARDY : std_logic;
SIGNAL N1515374 : std_logic;
SIGNAL ED12 : std_logic;
SIGNAL HOLDA : std_logic;
SIGNAL EA8 : std_logic;
SIGNAL ED11 : std_logic;
SIGNAL R_ED24 : std_logic;
SIGNAL EA7 : std_logic;
SIGNAL ED10 : std_logic;
SIGNAL R_ED23 : std_logic;
SIGNAL \DSP_TRST#\ : std_logic;
SIGNAL EA6 : std_logic;
SIGNAL DSP_HD8 : std_logic;
SIGNAL EA5 : std_logic;
SIGNAL NMI : std_logic;
SIGNAL N1515650 : std_logic;
SIGNAL R_EA4 : std_logic;
SIGNAL R_EA6 : std_logic;
SIGNAL R_ECLKOUT : std_logic;
SIGNAL ED9 : std_logic;
SIGNAL EA4 : std_logic;
SIGNAL R_EA5 : std_logic;
SIGNAL R_AWE : std_logic;
SIGNAL ED8 : std_logic;
SIGNAL ED0 : std_logic;
SIGNAL EA3 : std_logic;
SIGNAL GP_INT7 : std_logic;
SIGNAL ED26 : std_logic;
SIGNAL EA16 : std_logic;
SIGNAL GP_INT6 : std_logic;
SIGNAL ECLKOUT : std_logic;
SIGNAL DSP_TCK : std_logic;
SIGNAL R_ARE : std_logic;
SIGNAL EA15 : std_logic;
SIGNAL CLKOUT2 : std_logic;
SIGNAL ED19 : std_logic;
SIGNAL EA14 : std_logic;
SIGNAL ED18 : std_logic;
SIGNAL N1515548 : std_logic;
SIGNAL DSP_TDO : std_logic;
SIGNAL EA13 : std_logic;
SIGNAL ED17 : std_logic;
SIGNAL GP_INT5 : std_logic;
SIGNAL EA12 : std_logic;
SIGNAL CKE : std_logic;
SIGNAL ED16 : std_logic;
SIGNAL DSP_PLLHV : std_logic;
SIGNAL ED15 : std_logic;
SIGNAL DSP_GP13 : std_logic;
SIGNAL DSP_GP15 : std_logic;
SIGNAL N256686 : std_logic;
SIGNAL VCC3V3 : std_logic;
SIGNAL DSP_CLKIN : std_logic;
SIGNAL CS4272_SCLK : std_logic;
SIGNAL REF4_OUT : std_logic;
SIGNAL N1166110 : std_logic;
SIGNAL CS4272_LRCLK : std_logic;
SIGNAL CS4272_MCLK : std_logic;
SIGNAL CS4272_SDIN : std_logic;
SIGNAL REF2_OUT : std_logic;
SIGNAL REF_OUT : std_logic;
SIGNAL VCC5V : std_logic;
SIGNAL CS_AOUT_RN : std_logic;
SIGNAL N261524 : std_logic;
SIGNAL CS_AIN_LN : std_logic;
SIGNAL VCC1V2 : std_logic;
SIGNAL SDA_M1 : std_logic;
SIGNAL CS_AIN_LP : std_logic;
SIGNAL N1026167 : std_logic;
SIGNAL CS_AIN_RP : std_logic;
SIGNAL N1041204 : std_logic;
SIGNAL SCL_M0 : std_logic;
SIGNAL N1021779 : std_logic;
SIGNAL SCL0 : std_logic;
SIGNAL CS_AIN_RN : std_logic;
SIGNAL MCBSP_CLKIN : std_logic;
SIGNAL SDA0 : std_logic;
SIGNAL CS4272_SDOUT : std_logic;
SIGNAL FSX1 : std_logic;
SIGNAL MSMODE : std_logic;
SIGNAL CLKS1_SCL1 : std_logic;
SIGNAL CLKX1 : std_logic;
SIGNAL DX1 : std_logic;
SIGNAL CS_AOUT_LN : std_logic;
SIGNAL N257675 : std_logic;
SIGNAL DR1_SDA1 : std_logic;
SIGNAL GND : std_logic;
SIGNAL CS_AOUT_LP : std_logic;
SIGNAL CS_AOUT_RP : std_logic;
SIGNAL VCC12VP : std_logic;
SIGNAL VCC12VN : std_logic;
SIGNAL N1022674 : std_logic;
SIGNAL N1166296 : std_logic;
SIGNAL N1166483 : std_logic;
SIGNAL CS4272_RESET : std_logic;
SIGNAL N1028649 : std_logic;
SIGNAL FSR1 : std_logic;

-- INSTANCE ATTRIBUTES

ATTRIBUTE \PACKAGE\:string;
ATTRIBUTE \PACKAGE\ of N4 : label is "4";
ATTRIBUTE \PACKAGE\ of N5 : label is "5";
ATTRIBUTE \PACKAGE\ of U6 : label is "1";
ATTRIBUTE \PACKAGE\ of N1 : label is "1";
ATTRIBUTE \PACKAGE\ of N2 : label is "3";
ATTRIBUTE \PACKAGE\ of N3 : label is "2";


-- GATE INSTANCES

BEGIN
R89 : \15K\	PORT MAP(
	\1\ => N74104, 
	\2\ => GND
);
R25 : RS4	PORT MAP(
	\1\ => ED8, 
	\2\ => ED9, 
	\3\ => ED10, 
	\4\ => ED11, 
	\5\ => R_ED11, 
	\6\ => R_ED10, 
	\7\ => R_ED9, 
	\8\ => R_ED8
);
N4 : NE5532	PORT MAP(
	\AIN-\ => N10740, 
	\AIN+\ => N10593, 
	AOUT => N10780, 
	VCC => VCC12VP, 
	GND => VCC12VN, 
	\BIN+\ => N11845, 
	\BIN-\ => N11082, 
	BOUT => N11209
);
R57 : \10K\	PORT MAP(
	\1\ => HOLDA, 
	\2\ => VCC3V3
);
N5 : NE5532	PORT MAP(
	\AIN-\ => N44356, 
	\AIN+\ => N44344, 
	AOUT => N43972, 
	VCC => VCC12VP, 
	GND => VCC12VN, 
	\BIN+\ => N43948, 
	\BIN-\ => N44000, 
	BOUT => N43908
);
R26 : RS4	PORT MAP(
	\1\ => EA6, 
	\2\ => EA7, 
	\3\ => EA8, 
	\4\ => EA9, 
	\5\ => R_EA9, 
	\6\ => R_EA8, 
	\7\ => R_EA7, 
	\8\ => R_EA6
);
R58 : \10K\	PORT MAP(
	\1\ => ARDY, 
	\2\ => VCC3V3
);
R27 : RS4	PORT MAP(
	\1\ => ED12, 
	\2\ => ED13, 
	\3\ => ED14, 
	\4\ => ED15, 
	\5\ => R_ED15, 
	\6\ => R_ED14, 
	\7\ => R_ED13, 
	\8\ => R_ED12
);
R59 : \10K\	PORT MAP(
	\1\ => N2240979, 
	\2\ => GND
);
E1 : \EMI FILTER\	PORT MAP(
	I => DSP_PLL_FB, 
	GND => GND, 
	O => DSP_PLLHV
);
R28 : RS4	PORT MAP(
	\1\ => EA10, 
	\2\ => EA11, 
	\3\ => EA12, 
	\4\ => EA13, 
	\5\ => R_EA13, 
	\6\ => R_EA12, 
	\7\ => R_EA11, 
	\8\ => R_EA10
);
R29 : RS4	PORT MAP(
	\1\ => ED16, 
	\2\ => ED17, 
	\3\ => ED18, 
	\4\ => ED19, 
	\5\ => R_ED19, 
	\6\ => R_ED18, 
	\7\ => R_ED17, 
	\8\ => R_ED16
);
R100 : \634\	PORT MAP(
	\1\ => N11082, 
	\2\ => CS_AIN_LN
);
R101 : \100K\	PORT MAP(
	\1\ => N44344, 
	\2\ => N43948
);
R102 : \3.3K\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => N11845
);
R103 : \3.3K\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => N43948
);
R104 : \91\	PORT MAP(
	\1\ => N43908, 
	\2\ => CS_AIN_RN
);
R105 : \91\	PORT MAP(
	\1\ => N11209, 
	\2\ => CS_AIN_LN
);
R106 : \3.3K\	PORT MAP(
	\1\ => N11845, 
	\2\ => GND
);
R107 : \3.3K\	PORT MAP(
	\1\ => N43948, 
	\2\ => GND
);
C80 : \100nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C140 : \1uF\	PORT MAP(
	\1\ => N10593, 
	\2\ => LIN
);
C81 : \100nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C50 : \220nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C141 : \2700pF\	PORT MAP(
	\1\ => CS_AIN_LP, 
	\2\ => CS_AIN_LN
);
C82 : \100nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C142 : \2700pF\	PORT MAP(
	\1\ => CS_AIN_RP, 
	\2\ => CS_AIN_RN
);
C83 : \10nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C110 : \220pF\	PORT MAP(
	\1\ => GND, 
	\2\ => N66431
);
C51 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C84 : \10nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C111 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VP
);
C143 : \470pF\	PORT MAP(
	\1\ => N44000, 
	\2\ => N43908
);
C20 : \0.1uF\	PORT MAP(
	\1\ => N1022674, 
	\2\ => GND
);
C52 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C144 : \470pF\	PORT MAP(
	\1\ => N11082, 
	\2\ => N11209
);
C53 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C112 : \10uF\	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => GND
);
C21 : \0.1uF\	PORT MAP(
	\1\ => N1026167, 
	\2\ => GND
);
C85 : \10nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C86 : \10nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C145 : \10uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
C113 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C54 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C22 : \0.01uF\	PORT MAP(
	\1\ => N1022674, 
	\2\ => GND
);
R90 : \634\	PORT MAP(
	\1\ => N44356, 
	\2\ => CS_AIN_RP
);
C55 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C23 : \0.01uF\	PORT MAP(
	\1\ => N1026167, 
	\2\ => GND
);
R91 : \634\	PORT MAP(
	\1\ => N10740, 
	\2\ => CS_AIN_LP
);
C114 : \10uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
C87 : \10nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
C146 : \0.01uF\	PORT MAP(
	\1\ => GND, 
	\2\ => N11845
);
C56 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C24 : \47uF\	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => GND
);
U1 : CS4272	PORT MAP(
	XTO => OPEN, 
	XTI => GND, 
	MCCLK => CS4272_MCLK, 
	LRCK => CS4272_LRCLK, 
	SCLK => CS4272_SCLK, 
	SDOUT => MSMODE, 
	SDIN => CS4272_SDIN, 
	DGND => GND, 
	VD => VCC3V3, 
	VL => VCC3V3, 
	\SCL/CCLK\ => SCL_M0, 
	\SDA/CDIN\ => SDA_M1, 
	\AD0/C\\S\\\ => GND, 
	\R\\S\\T\\\ => CS4272_RESET, 
	VCOM => N261524, 
	\AINA-\ => CS_AIN_LN, 
	\AINA+\ => CS_AIN_LP, 
	\AINB+\ => CS_AIN_RP, 
	\AINB-\ => CS_AIN_RN, 
	VA => N256686, 
	AGND => GND, 
	\FILT+\ => N257675, 
	\A\\M\\U\\T\\E\\C\\\ => OPEN, 
	\AOUTA-\ => CS_AOUT_LN, 
	\AOUTA+\ => CS_AOUT_LP, 
	\AOUTB+\ => CS_AOUT_RP, 
	\AOUTB-\ => CS_AOUT_RN, 
	\B\\M\\U\\T\\E\\C\\\ => OPEN
);
R60 : \15K\	PORT MAP(
	\1\ => N48145, 
	\2\ => N52922
);
C147 : \100uF\	PORT MAP(
	\1\ => N11845, 
	\2\ => GND
);
C115 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VP
);
C88 : \10nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R92 : \91\	PORT MAP(
	\1\ => N43972, 
	\2\ => CS_AIN_RP
);
C25 : \47uF\	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => GND
);
C89 : \1nF\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => GND
);
R93 : \91\	PORT MAP(
	\1\ => N10780, 
	\2\ => CS_AIN_LP
);
C148 : \0.1uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
U2 : AMS1117_3V3	PORT MAP(
	\GND/ADJ\ => GND, 
	VOUT => VCC3V3, 
	VIN => VCC5V, 
	TAB => TAB
);
R61 : \15K\	PORT MAP(
	\1\ => N75509, 
	\2\ => N81989
);
C116 : \10uF\	PORT MAP(
	\1\ => VCC12VP, 
	\2\ => GND
);
C57 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
R94 : \100K\	PORT MAP(
	\1\ => LIN, 
	\2\ => GND
);
U3 : AMS1117_ADJ	PORT MAP(
	\GND/ADJ\ => N1041204, 
	VOUT => VCC1V2, 
	VIN => VCC5V, 
	TAB => TAB
);
C117 : \0.1uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
R1 : \47K\	PORT MAP(
	\1\ => VCC3V3, 
	\2\ => MSMODE
);
C149 : \10uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
R30 : RS4	PORT MAP(
	\1\ => EA14, 
	\2\ => EA15, 
	\3\ => EA16, 
	\4\ => EA17, 
	\5\ => R_EA17, 
	\6\ => R_EA16, 
	\7\ => R_EA15, 
	\8\ => R_EA14
);
C58 : \22nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
C26 : \47uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
R62 : \3K\	PORT MAP(
	\1\ => CS_AOUT_LN, 
	\2\ => N47737
);
R63 : \12K\	PORT MAP(
	\1\ => N47737, 
	\2\ => N48145
);
R2 : \33\	PORT MAP(
	\1\ => CS4272_SDOUT, 
	\2\ => MSMODE
);
C118 : \10uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
R95 : \634\	PORT MAP(
	\1\ => N10780, 
	\2\ => N11082
);
C59 : \2.2nF\	PORT MAP(
	\1\ => VCC1V2, 
	\2\ => GND
);
R31 : \1K\	PORT MAP(
	\1\ => CKE, 
	\2\ => VCC3V3
);
U4 : CLOCK	PORT MAP(
	NC => OPEN, 
	GND => GND, 
	CLK => N1021779, 
	VCC => N1022674
);
C27 : \47uF\	PORT MAP(
	\1\ => VCC5V, 
	\2\ => GND
);
R96 : \100K\	PORT MAP(
	\1\ => RIN, 
	\2\ => GND
);
R64 : \3K\	PORT MAP(
	\1\ => N48145, 
	\2\ => N52333
);
C28 : \47uF\	PORT MAP(
	\1\ => GND, 
	\2\ => VCC12VN
);
R32 : RS4	PORT MAP(
	\1\ => ED20,