dsp6713_mcbsp.c

于博士cadence视频配套工程文件

/* ------------------------------------------------------------------ */
/* Copyright declaration                                              */
/* ------------------------------------------------------------------ */
/* ------------------------------------------------------------------ */
/* FileName		:         	my_mcbsp_start.c                          */
/* Writen by	:       	Yu zheng                                  */ 
/* ------------------------------------------------------------------ */

#define CHIP_6713

/* Include header file */
#include <c6x.h>
#include <csl.h>
#include <csl_mcbsp.h>

#include "DSP6713_EDMA.h"
#include "DSP6713_MCBSP.h"

/*********************************************************/
/* define mcbsp handle */
extern MCBSP_Handle hMcbsp0;
extern MCBSP_Handle hMcbsp1;

MCBSP_Handle hMcbsp;
/*******************************************************/
/* mcbsp config structure */
MCBSP_Config MyConfig_mcbsp = {
		
		MCBSP_SPCR_RMK(						/* spcr */
			MCBSP_SPCR_FREE_DEFAULT,
			MCBSP_SPCR_SOFT_DEFAULT,
			MCBSP_SPCR_FRST_YES,		
			MCBSP_SPCR_GRST_YES,				
			MCBSP_SPCR_XINTM_XRDY,	//	
			MCBSP_SPCR_XSYNCERR_NO,
			MCBSP_SPCR_XRST_YES,
			MCBSP_SPCR_DLB_OFF,			
			MCBSP_SPCR_RJUST_LZF,			/*Left-justify and zero-fill LSBs in DRR*/		
			MCBSP_SPCR_CLKSTP_DISABLE,
			MCBSP_SPCR_DXENA_OFF,
			MCBSP_SPCR_RINTM_RRDY,		
			MCBSP_SPCR_RSYNCERR_NO,
			MCBSP_SPCR_RRST_YES
			),
				
		MCBSP_RCR_RMK(						/* rcr */
			MCBSP_RCR_RPHASE_SINGLE,
			MCBSP_RCR_RFRLEN2_DEFAULT,
			MCBSP_RCR_RWDLEN2_DEFAULT,			
			MCBSP_RCR_RCOMPAND_MSB,
			MCBSP_RCR_RFIG_YES,
			MCBSP_RCR_RDATDLY_0BIT,
			MCBSP_RCR_RFRLEN1_OF(1),
			MCBSP_RCR_RWDLEN1_32BIT,
			MCBSP_RCR_RWDREVRS_DISABLE
			),
				
		MCBSP_XCR_RMK(						/* xcr */
			MCBSP_XCR_XPHASE_SINGLE,
			MCBSP_XCR_XFRLEN2_DEFAULT,
			MCBSP_XCR_XWDLEN2_DEFAULT,
			MCBSP_XCR_XCOMPAND_MSB,				
			MCBSP_XCR_XFIG_YES,
			MCBSP_XCR_XDATDLY_0BIT,
			MCBSP_XCR_XFRLEN1_OF(1),
			MCBSP_XCR_XWDLEN1_32BIT,
			MCBSP_XCR_XWDREVRS_DISABLE
			),
				
		MCBSP_SRGR_RMK(						/* srgr */
			MCBSP_SRGR_GSYNC_FREE,
			MCBSP_SRGR_CLKSP_DEFAULT,
			MCBSP_SRGR_CLKSM_CLKS,			// sample rate gen driven by CLKS pin 12.288MHz
			MCBSP_SRGR_FSGM_FSG,
			MCBSP_SRGR_FPER_OF(63),
			MCBSP_SRGR_FWID_OF(31),
			MCBSP_SRGR_CLKGDV_OF(3)  		// 12.288/4 = 3.072MHz
			),
		
        MCBSP_MCR_DEFAULT,					/* mcr */
		
        MCBSP_RCER_DEFAULT,					/* rcer */
		
        MCBSP_XCER_DEFAULT,					/* xcer */
		
     	MCBSP_PCR_RMK(						/* pcr */
			MCBSP_PCR_XIOEN_SP,
			MCBSP_PCR_RIOEN_SP,
			MCBSP_PCR_FSXM_INTERNAL,	
			MCBSP_PCR_FSRM_EXTERNAL, 	
			MCBSP_PCR_CLKXM_OUTPUT,
			MCBSP_PCR_CLKRM_INPUT,  
			MCBSP_PCR_CLKSSTAT_DEFAULT,
			MCBSP_PCR_DXSTAT_DEFAULT,
			MCBSP_PCR_FSXP_DEFAULT,
			MCBSP_PCR_FSRP_ACTIVEHIGH,
			MCBSP_PCR_CLKXP_FALLING,    // must be falling for 4272
			MCBSP_PCR_CLKRP_RISING 
			)
};

/****************************************************************/
void my_mcbsp_start(Uint32 mcbsp_num)
{
	Uint32 wait = 0;

	#if (mcbsp_num == mcbsp0)			/* config the the McBSP0 registers*/					
		hMcbsp0 = MCBSP_open(MCBSP_DEV0,MCBSP_OPEN_RESET);
		MCBSP_config(hMcbsp0, &MyConfig_mcbsp);   	         	
		hMcbsp = hMcbsp0;		
		for (wait=0; wait<2; wait++); 	/* Wait two CLKSRG */
	#endif

	#if (mcbsp_num == mcbsp1)			/* config the the McBSP1 registers*/						
		hMcbsp1 = MCBSP_open(MCBSP_DEV1,MCBSP_OPEN_RESET);
		MCBSP_config(hMcbsp1, &MyConfig_mcbsp);          	
		hMcbsp = hMcbsp1;		
		for (wait=0; wait<2; wait++); 	/* Wait two CLKSRG */
	#endif

	
	/* Enable sample rate generator : set GRST# = 1 */ 
	MCBSP_enableSrgr(hMcbsp);	
	for (wait=0; wait<8; wait++); 		/* Wait two CLKGs */
	
	my_edma_start();

	/* take the section (frame sync is an input) out of reset */ 
	MCBSP_enableRcv(hMcbsp);

	/* clear potential XSYNCERR after chip reset */
	MCBSP_enableXmt(hMcbsp);	
	for (wait=0; wait<8; wait++); 		/* Wait two CLKGs */
	MCBSP_FSETH(hMcbsp,SPCR,XRST,0);

	/* take the frame master out of reset */ 
	MCBSP_enableXmt(hMcbsp);

	/* If FSGM=1, enable frame generator by setting FRST=1 */
	MCBSP_enableFsync(hMcbsp);

}   
/*****************************************
* end of my_mcbsp_start.c 
******************************************/