dsp6713_chip.c

于博士cadence视频配套工程文件

/* ------------------------------------------------------------------ */
/* Copyright declaration                                              */
/* ------------------------------------------------------------------ */
/* ------------------------------------------------------------------ */
/* FileName:        DSP6713_CHIP.c                                    */
/* Writen by:       Yu zheng                                          */ 
/* ------------------------------------------------------------------ */

#define CHIP_6713

/* Include header files */
#include <c6x.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_pll.h>
#include "DSP6713_CHIP.h"

/* ------------------------------------------------------------------ */
static void PLLDelay(Uint32 count)
{
   Uint32 i = count;
   while(i--)
   {
     asm(" NOP 1");
   }
}

/* ------------------------------------------------------------------ */
static void initPLL()
{
	// temporarily disable global interrupts 
	Uint32 gie;
	gie = IRQ_globalDisable();

	//******************  Initialize PLL Registers *****************         
	// Put PLL in bypass
	PLL_bypass();
	PLLDelay(20);
	
	// Reset PLL
	PLL_reset();
	PLLDelay(20);
	
	// Set main multiplier/divisor
    PLL_RSET(PLLDIV0,
    		 PLL_PLLDIV0_RMK(PLL_PLLDIV0_D0EN_ENABLE, PLL_PLLDIV0_RATIO_OF(0))
    		 );                           // 12.288/1 = 12.288 MHz

 	PLL_RSET(PLLM, PLL_PLLM_PLLM_OF(17)); // 12.288*17 = 208 MHz 
 						 

    // Set DSP clock 
    PLL_RSET(PLLDIV1,
    		 PLL_PLLDIV1_RMK(PLL_PLLDIV1_D1EN_ENABLE, PLL_PLLDIV1_RATIO_OF(0))
    		 ); 						 // 208/1 = 208 MHz 
    PLLDelay(20);    

    // Set peripheral clock 
    PLL_RSET(PLLDIV2, 
    		 PLL_PLLDIV2_RMK(PLL_PLLDIV2_D2EN_ENABLE, PLL_PLLDIV2_RATIO_OF(1))
    		 ); 						 // 208/2 = 104 MHz 
    PLLDelay(20);
    
    // Set EMIF clock 
    PLL_RSET(PLLDIV3,
    		 PLL_PLLDIV3_RMK(PLL_PLLDIV3_D3EN_DISABLE, PLL_PLLDIV3_RATIO_OF(1))
    		 ); 						// 208/2 = 104 MHz 
    PLLDelay(20);
    
    PLL_RSET(OSCDIV1,
    		 PLL_OSCDIV1_RMK(PLL_OSCDIV1_OD1EN_ENABLE,PLL_OSCDIV1_RATIO_OF(1))
    		 ); 						// 208/2 = 104 MHz
    
    // Take PLL out of reset. Wait for PLL to lock
    PLL_deassert();
    PLLDelay(1500);
    
    // Enalbe PLL 
    PLL_enable();
    PLLDelay(20);

	// restore global interrupts back 
	IRQ_globalRestore(gie);

}  // end of initPLL

/* ------------------------------------------------------------------ */
void DSP6713_chipinit()
{
	/* register DEVCFG */
	CHIP_Config MyChipConfig =
	{
		CHIP_DEVCFG_RMK(
						CHIP_DEVCFG_EKSRC_SYSCLK3,
						CHIP_DEVCFG_TOUT1SEL_TOUT1PIN,
						CHIP_DEVCFG_TOUT0SEL_TOUT0PIN,
						CHIP_DEVCFG_MCBSP0DIS_0,
						CHIP_DEVCFG_MCBSP1DIS_0
	   					) 
	};
	CHIP_config(&MyChipConfig);

	initPLL();
}

/* ------------------------------------------------------------------ */
/* end of DSP6713_init.c                                              */
/* ------------------------------------------------------------------ */